hdl._ast: add SwitchValue, reimplement ArrayProxy with it.
This commit is contained in:
Wanda
Catherine
parent
2eb62a8b49
commit
2cf9bbf306
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@ -18,7 +18,7 @@ from .._unused import *
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__all__ = [
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"SyntaxError", "SyntaxWarning",
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"Shape", "signed", "unsigned", "ShapeCastable", "ShapeLike",
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"Value", "Const", "C", "AnyConst", "AnySeq", "Operator", "Mux", "Part", "Slice", "Cat", "Concat",
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"Value", "Const", "C", "AnyConst", "AnySeq", "Operator", "Mux", "Part", "Slice", "Cat", "Concat", "SwitchValue",
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"Array", "ArrayProxy",
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"Signal", "ClockSignal", "ResetSignal",
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"ValueCastable", "ValueLike",
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@ -1892,6 +1892,60 @@ class Concat(Value):
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return "(cat {})".format(" ".join(map(repr, self.parts)))
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@final
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class SwitchValue(Value):
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def __init__(self, test, cases, *, src_loc=None, src_loc_at=0):
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if src_loc is None:
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super().__init__(src_loc_at=src_loc_at)
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else:
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self.src_loc = src_loc
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self._test = Value.cast(test)
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new_cases = []
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for patterns, value in cases:
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if patterns is not None:
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if not isinstance(patterns, tuple):
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patterns = (patterns,)
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new_patterns = ()
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key_mask = (1 << len(self.test)) - 1
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for key in _normalize_patterns(patterns, self._test.shape()):
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if isinstance(key, int):
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key = to_binary(key & key_mask, len(self.test))
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new_patterns = (*new_patterns, key)
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else:
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new_patterns = None
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new_cases.append((new_patterns, Value.cast(value)))
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self._cases = tuple(new_cases)
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@property
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def test(self):
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return self._test
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@property
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def cases(self):
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return self._cases
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def shape(self):
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return Shape._unify(value.shape() for _patterns, value in self._cases)
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def _lhs_signals(self):
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return union((value._lhs_signals() for _patterns, value in self.cases), start=SignalSet())
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def _rhs_signals(self):
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signals = union((value._rhs_signals() for _patterns, value in self.cases), start=SignalSet())
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return self.test._rhs_signals() | signals
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def __repr__(self):
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def case_repr(patterns, value):
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if patterns is None:
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return f"(default {value!r})"
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elif len(patterns) == 1:
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return f"(case {patterns[0]} {value!r})"
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else:
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return "(case ({}) {!r})".format(" ".join(patterns), value)
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case_reprs = (case_repr(patterns, value) for patterns, value in self.cases)
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return "(switch-value {!r} {})".format(self.test, " ".join(case_reprs))
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class _SignalMeta(ABCMeta):
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def __call__(cls, shape=None, src_loc_at=0, **kwargs):
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signal = super().__call__(shape, **kwargs, src_loc_at=src_loc_at + 1)
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@ -2356,10 +2410,17 @@ class Array(MutableSequence):
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", ".join(map(repr, self._inner)))
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def _proxy_value(name):
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@functools.wraps(getattr(Value, name))
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def inner(self, *args, **kwargs):
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return getattr(Value.cast(self), name)(*args, **kwargs)
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return inner
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@final
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class ArrayProxy(Value):
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class ArrayProxy(ValueCastable):
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def __init__(self, elems, index, *, src_loc_at=0):
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super().__init__(src_loc_at=1 + src_loc_at)
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self.src_loc = tracer.get_src_loc(1 + src_loc_at)
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self._elems = elems
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self._index = Value.cast(index)
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@ -2385,19 +2446,73 @@ class ArrayProxy(Value):
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# elements. I.e., shape-wise, an array proxy must be identical to an equivalent mux tree.
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return Shape._unify(elem.shape() for elem in self._iter_as_values())
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def _lhs_signals(self):
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signals = union((elem._lhs_signals() for elem in self._iter_as_values()),
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start=SignalSet())
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return signals
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def as_value(self):
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return SwitchValue(
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self._index,
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(
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(index, value)
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for index, value in enumerate(self._elems)
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if index in range(1 << len(self._index))
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),
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src_loc=self.src_loc,
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)
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def _rhs_signals(self):
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signals = union((elem._rhs_signals() for elem in self._iter_as_values()),
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start=SignalSet())
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return self.index._rhs_signals() | signals
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def eq(self, value, *, src_loc_at=0):
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return self.as_value().eq(value, src_loc_at=1 + src_loc_at)
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def __repr__(self):
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return "(proxy (array [{}]) {!r})".format(", ".join(map(repr, self.elems)), self.index)
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as_signed = _proxy_value("as_signed")
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as_unsigned = _proxy_value("as_unsigned")
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__len__ = _proxy_value("__len__")
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__bool__ = _proxy_value("__bool__")
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bool = _proxy_value("bool")
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__pos__ = _proxy_value("__pos__")
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__neg__ = _proxy_value("__neg__")
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__add__ = _proxy_value("__add__")
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__radd__ = _proxy_value("__radd__")
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__sub__ = _proxy_value("__sub__")
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__rsub__ = _proxy_value("__rsub__")
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__mul__ = _proxy_value("__mul__")
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__rmul__ = _proxy_value("__rmul__")
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__floordiv__ = _proxy_value("__floordiv__")
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__rfloordiv__ = _proxy_value("__rfloordiv__")
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__mod__ = _proxy_value("__mod__")
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__rmod__ = _proxy_value("__rmod__")
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__eq__ = _proxy_value("__eq__")
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__ne__ = _proxy_value("__ne__")
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__lt__ = _proxy_value("__lt__")
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__le__ = _proxy_value("__le__")
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__gt__ = _proxy_value("__gt__")
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__ge__ = _proxy_value("__ge__")
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__abs__ = _proxy_value("__abs__")
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__invert__ = _proxy_value("__invert__")
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__and__ = _proxy_value("__and__")
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__rand__ = _proxy_value("__rand__")
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__or__ = _proxy_value("__or__")
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__ror__ = _proxy_value("__ror__")
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__xor__ = _proxy_value("__xor__")
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__rxor__ = _proxy_value("__rxor__")
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any = _proxy_value("any")
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all = _proxy_value("all")
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xor = _proxy_value("xor")
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implies = _proxy_value("implies")
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__lshift__ = _proxy_value("__lshift__")
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__rlshift__ = _proxy_value("__rlshift__")
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__rshift__ = _proxy_value("__rshift__")
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__rrshift__ = _proxy_value("__rrshift__")
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shift_left = _proxy_value("shift_left")
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shift_right = _proxy_value("shift_right")
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rotate_left = _proxy_value("rotate_left")
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rotate_right = _proxy_value("rotate_right")
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__contains__ = _proxy_value("__contains__")
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bit_select = _proxy_value("bit_select")
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word_select = _proxy_value("word_select")
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replicate = _proxy_value("replicate")
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matches = _proxy_value("matches")
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__format__ = _proxy_value("__format__")
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@final
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class Initial(Value):
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@ -2772,7 +2887,7 @@ class Switch(Statement):
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self.src_loc = src_loc
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self._test = Value.cast(test)
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self._cases = []
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new_cases = []
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for patterns, stmts, case_src_loc in cases:
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if patterns is not None:
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# Map: key -> (key,); (key...) -> (key...)
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@ -2787,10 +2902,8 @@ class Switch(Statement):
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new_patterns = (*new_patterns, key)
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else:
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new_patterns = None
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if not isinstance(stmts, Iterable):
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stmts = [stmts]
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self._cases.append((new_patterns, Statement.cast(stmts), case_src_loc))
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self._cases = tuple(self._cases)
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new_cases.append((new_patterns, Statement.cast(stmts), case_src_loc))
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self._cases = tuple(new_cases)
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@property
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def test(self):
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@ -2816,7 +2929,7 @@ class Switch(Statement):
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return f"(case {patterns[0]} {stmts_repr})"
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else:
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return "(case ({}) {})".format(" ".join(patterns), stmts_repr)
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case_reprs = [case_repr(patterns, stmts) for patterns, stmts, _src_loc in self.cases]
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case_reprs = (case_repr(patterns, stmts) for patterns, stmts, _src_loc in self.cases)
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return "(switch {!r} {})".format(self.test, " ".join(case_reprs))
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@ -885,30 +885,39 @@ class NetlistEmitter:
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stride=value.stride, offset=offset, src_loc=value.src_loc)
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result = self.netlist.add_value_cell(value.width, cell)
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signed = False
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elif isinstance(value, _ast.ArrayProxy):
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elems = [self.emit_rhs(module_idx, elem) for elem in value.elems]
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elif isinstance(value, _ast.SwitchValue):
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test, _signed = self.emit_rhs(module_idx, value.test)
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conds = []
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elems = []
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for patterns, elem, in value.cases:
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if patterns is not None:
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if not patterns:
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# Hack: empty pattern set cannot be supported by RTLIL.
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continue
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for pattern in patterns:
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assert len(pattern) == len(test)
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cell = _nir.Matches(module_idx, value=test, patterns=patterns,
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src_loc=value.src_loc)
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net, = self.netlist.add_value_cell(1, cell)
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conds.append(net)
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else:
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conds.append(_nir.Net.from_const(1))
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elems.append(self.emit_rhs(module_idx, elem))
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cell = _nir.PriorityMatch(module_idx, en=_nir.Net.from_const(1),
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inputs=_nir.Value(conds),
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src_loc=value.src_loc)
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conds = self.netlist.add_value_cell(len(conds), cell)
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shape = _ast.Shape._unify(
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_ast.Shape(len(value), signed)
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for value, signed in elems
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)
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elems = tuple(self.extend(elem, elem_signed, shape.width) for elem, elem_signed in elems)
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index, _signed = self.emit_rhs(module_idx, value.index)
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conds = []
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for case_index in range(len(elems)):
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cell = _nir.Matches(module_idx, value=index,
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patterns=(to_binary(case_index, len(index)),),
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src_loc=value.src_loc)
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subcond, = self.netlist.add_value_cell(1, cell)
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conds.append(subcond)
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conds = _nir.Value(conds)
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cell = _nir.PriorityMatch(module_idx, en=_nir.Net.from_const(1), inputs=conds, src_loc=value.src_loc)
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conds = self.netlist.add_value_cell(len(conds), cell)
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assignments = [
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_nir.Assignment(cond=cond, start=0, value=elem, src_loc=value.src_loc)
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for cond, elem in zip(conds, elems)
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_nir.Assignment(cond=subcond, start=0, value=elem, src_loc=value.src_loc)
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for subcond, elem in zip(conds, elems)
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]
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cell = _nir.AssignmentList(module_idx, default=elems[0], assignments=assignments,
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src_loc=value.src_loc)
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cell = _nir.AssignmentList(module_idx, default=_nir.Value.from_const(0, shape.width),
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assignments=assignments, src_loc=value.src_loc)
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result = self.netlist.add_value_cell(shape.width, cell)
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signed = shape.signed
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elif isinstance(value, _ast.Concat):
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@ -1017,19 +1026,29 @@ class NetlistEmitter:
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else:
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subrhs = rhs
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self.emit_assign(module_idx, cd, lhs.value, start, subrhs, subcond, src_loc=src_loc)
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elif isinstance(lhs, _ast.ArrayProxy):
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index, _signed = self.emit_rhs(module_idx, lhs.index)
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elif isinstance(lhs, _ast.SwitchValue):
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test, _signed = self.emit_rhs(module_idx, lhs.test)
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conds = []
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for case_index in range(len(lhs.elems)):
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cell = _nir.Matches(module_idx, value=index,
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patterns=(to_binary(case_index, len(index)),),
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src_loc=lhs.src_loc)
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subcond, = self.netlist.add_value_cell(1, cell)
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conds.append(subcond)
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elems = []
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for patterns, elem in lhs.cases:
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if patterns is not None:
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if not patterns:
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# Hack: empty pattern set cannot be supported by RTLIL.
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continue
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for pattern in patterns:
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assert len(pattern) == len(test)
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cell = _nir.Matches(module_idx, value=test, patterns=patterns,
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src_loc=lhs.src_loc)
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net, = self.netlist.add_value_cell(1, cell)
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conds.append(net)
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else:
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conds.append(_nir.Net.from_const(1))
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elems.append(elem)
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conds = _nir.Value(conds)
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cell = _nir.PriorityMatch(module_idx, en=cond, inputs=conds, src_loc=lhs.src_loc)
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cell = _nir.PriorityMatch(module_idx, en=_nir.Net.from_const(1),
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inputs=conds, src_loc=lhs.src_loc)
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conds = self.netlist.add_value_cell(len(conds), cell)
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for subcond, val in zip(conds, lhs.elems):
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for subcond, val in zip(conds, elems):
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self.emit_assign(module_idx, cd, val, lhs_start, rhs[:len(val)], subcond, src_loc=src_loc)
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elif isinstance(lhs, _ast.Operator):
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assert lhs.operator in ('u', 's')
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@ -58,7 +58,7 @@ class ValueVisitor(metaclass=ABCMeta):
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pass # :nocov:
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@abstractmethod
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def on_ArrayProxy(self, value):
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def on_SwitchValue(self, value):
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pass # :nocov:
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@abstractmethod
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@ -90,8 +90,8 @@ class ValueVisitor(metaclass=ABCMeta):
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new_value = self.on_Part(value)
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elif type(value) is Concat:
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new_value = self.on_Concat(value)
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elif type(value) is ArrayProxy:
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new_value = self.on_ArrayProxy(value)
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elif type(value) is SwitchValue:
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new_value = self.on_SwitchValue(value)
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elif type(value) is Initial:
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new_value = self.on_Initial(value)
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else:
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@ -133,9 +133,8 @@ class ValueTransformer(ValueVisitor):
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def on_Concat(self, value):
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return Concat(self.on_value(o) for o in value.parts)
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def on_ArrayProxy(self, value):
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return ArrayProxy([self.on_value(elem) for elem in value._iter_as_values()],
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self.on_value(value.index))
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def on_SwitchValue(self, value):
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return SwitchValue(self.on_value(value.test), [(patterns, self.on_value(val)) for patterns, val in value.cases])
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def on_Initial(self, value):
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return value
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@ -399,10 +398,10 @@ class DomainCollector(ValueVisitor, StatementVisitor):
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for o in value.parts:
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self.on_value(o)
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def on_ArrayProxy(self, value):
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for elem in value._iter_as_values():
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self.on_value(elem)
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self.on_value(value.index)
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def on_SwitchValue(self, value):
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self.on_value(value.test)
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for patterns, val in value.cases:
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self.on_value(val)
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def on_Initial(self, value):
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pass
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@ -67,6 +67,53 @@ class _Compiler:
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self.state = state
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self.emitter = emitter
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def _emit_switch(self, test, cases, case_handler):
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if not cases:
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return
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use_match = _USE_PATTERN_MATCHING
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for patterns, *_ in cases:
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if patterns is None:
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continue
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for pattern in patterns:
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if "-" in pattern:
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use_match = False
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if use_match:
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self.emitter.append(f"match {test}:")
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with self.emitter.indent():
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for case in cases:
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patterns = case[0]
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if patterns is None:
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self.emitter.append(f"case _:")
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elif not patterns:
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self.emitter.append(f"case _ if False:")
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else:
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self.emitter.append(f"case {' | '.join(f'0b0{pattern}' for pattern in patterns)}:")
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with self.emitter.indent():
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case_handler(*case)
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else:
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for index, case in enumerate(cases):
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patterns = case[0]
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gen_checks = []
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if patterns is None:
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gen_checks.append(f"True")
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elif not patterns:
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gen_checks.append(f"False")
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else:
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for pattern in patterns:
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if "-" in pattern:
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mask = int("".join("0" if b == "-" else "1" for b in pattern), 2)
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value = int("".join("0" if b == "-" else b for b in pattern), 2)
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gen_checks.append(f"{value} == ({mask} & {test})")
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else:
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value = int(pattern or "0", 2)
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gen_checks.append(f"{value} == {test}")
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if index == 0:
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self.emitter.append(f"if {' or '.join(gen_checks)}:")
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else:
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self.emitter.append(f"elif {' or '.join(gen_checks)}:")
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with self.emitter.indent():
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case_handler(*case)
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class _ValueCompiler(ValueVisitor, _Compiler):
|
||||
helpers = {
|
||||
|
|
@ -223,36 +270,13 @@ class _RHSValueCompiler(_ValueCompiler):
|
|||
return f"({' | '.join(gen_parts)})"
|
||||
return f"0"
|
||||
|
||||
def on_ArrayProxy(self, value):
|
||||
index_mask = (1 << len(value.index)) - 1
|
||||
gen_index = self.emitter.def_var("rhs_index", f"{index_mask:#x} & {self(value.index)}")
|
||||
gen_value = self.emitter.gen_var("rhs_proxy")
|
||||
if value.elems:
|
||||
if _USE_PATTERN_MATCHING:
|
||||
self.emitter.append(f"match {gen_index}:")
|
||||
with self.emitter.indent():
|
||||
for index, elem in enumerate(value.elems):
|
||||
self.emitter.append(f"case {index}:")
|
||||
with self.emitter.indent():
|
||||
self.emitter.append(f"{gen_value} = {self(elem)}")
|
||||
self.emitter.append("case _:")
|
||||
with self.emitter.indent():
|
||||
self.emitter.append(f"{gen_value} = {self(value.elems[-1])}")
|
||||
else:
|
||||
for index, elem in enumerate(value.elems):
|
||||
if index == 0:
|
||||
self.emitter.append(f"if {index} == {gen_index}:")
|
||||
else:
|
||||
self.emitter.append(f"elif {index} == {gen_index}:")
|
||||
with self.emitter.indent():
|
||||
self.emitter.append(f"{gen_value} = {self(elem)}")
|
||||
self.emitter.append(f"else:")
|
||||
with self.emitter.indent():
|
||||
self.emitter.append(f"{gen_value} = {self(value.elems[-1])}")
|
||||
|
||||
return gen_value
|
||||
else:
|
||||
return f"0"
|
||||
def on_SwitchValue(self, value):
|
||||
gen_test = self.emitter.def_var("test", f"{(1 << len(value.test)) - 1:#x} & {self(value.test)}")
|
||||
gen_value = self.emitter.def_var("rhs_switch", "0")
|
||||
def case_handler(patterns, elem):
|
||||
self.emitter.append(f"{gen_value} = {self(elem)}")
|
||||
self._emit_switch(gen_test, value.cases, case_handler)
|
||||
return gen_value
|
||||
|
||||
@classmethod
|
||||
def compile(cls, state, value, *, mode):
|
||||
|
|
@ -323,34 +347,12 @@ class _LHSValueCompiler(_ValueCompiler):
|
|||
offset += len(part)
|
||||
return gen
|
||||
|
||||
def on_ArrayProxy(self, value):
|
||||
def on_SwitchValue(self, value):
|
||||
def gen(arg):
|
||||
index_mask = (1 << len(value.index)) - 1
|
||||
gen_index = self.emitter.def_var("index", f"{self.rrhs(value.index)} & {index_mask:#x}")
|
||||
if value.elems:
|
||||
if _USE_PATTERN_MATCHING:
|
||||
self.emitter.append(f"match {gen_index}:")
|
||||
with self.emitter.indent():
|
||||
for index, elem in enumerate(value.elems):
|
||||
self.emitter.append(f"case {index}:")
|
||||
with self.emitter.indent():
|
||||
self(elem)(arg)
|
||||
self.emitter.append("case _:")
|
||||
with self.emitter.indent():
|
||||
self(value.elems[-1])(arg)
|
||||
else:
|
||||
for index, elem in enumerate(value.elems):
|
||||
if index == 0:
|
||||
self.emitter.append(f"if {index} == {gen_index}:")
|
||||
else:
|
||||
self.emitter.append(f"elif {index} == {gen_index}:")
|
||||
with self.emitter.indent():
|
||||
self(elem)(arg)
|
||||
self.emitter.append(f"else:")
|
||||
with self.emitter.indent():
|
||||
self(value.elems[-1])(arg)
|
||||
else:
|
||||
self.emitter.append(f"pass")
|
||||
gen_test = self.emitter.def_var("test", f"{(1 << len(value.test)) - 1:#x} & {self.rrhs(value.test)}")
|
||||
def case_handler(patterns, elem):
|
||||
self(elem)(arg)
|
||||
self._emit_switch(gen_test, value.cases, case_handler)
|
||||
return gen
|
||||
|
||||
|
||||
|
|
@ -396,27 +398,9 @@ class _StatementCompiler(StatementVisitor, _Compiler):
|
|||
def on_Switch(self, stmt):
|
||||
gen_test_value = self.rhs(stmt.test) # check for oversized value before generating mask
|
||||
gen_test = self.emitter.def_var("test", f"{(1 << len(stmt.test)) - 1:#x} & {gen_test_value}")
|
||||
for index, (patterns, stmts, _src_loc) in enumerate(stmt.cases):
|
||||
gen_checks = []
|
||||
if patterns is None:
|
||||
gen_checks.append(f"True")
|
||||
elif not patterns:
|
||||
gen_checks.append(f"False")
|
||||
else:
|
||||
for pattern in patterns:
|
||||
if "-" in pattern:
|
||||
mask = int("".join("0" if b == "-" else "1" for b in pattern), 2)
|
||||
value = int("".join("0" if b == "-" else b for b in pattern), 2)
|
||||
gen_checks.append(f"{value} == ({mask} & {gen_test})")
|
||||
else:
|
||||
value = int(pattern or "0", 2)
|
||||
gen_checks.append(f"{value} == {gen_test}")
|
||||
if index == 0:
|
||||
self.emitter.append(f"if {' or '.join(gen_checks)}:")
|
||||
else:
|
||||
self.emitter.append(f"elif {' or '.join(gen_checks)}:")
|
||||
with self.emitter.indent():
|
||||
self(stmts)
|
||||
def case_handler(pattern, stmt, src_loc):
|
||||
self(stmt)
|
||||
self._emit_switch(gen_test, stmt.cases, case_handler)
|
||||
|
||||
def emit_format(self, format):
|
||||
format_string = []
|
||||
|
|
|
|||
|
|
@ -1144,6 +1144,7 @@ class ArrayProxyTestCase(FHDLTestCase):
|
|||
s = Signal(range(3))
|
||||
v = a[s]
|
||||
self.assertEqual(repr(v), "(proxy (array [1, 2, 3]) (sig s))")
|
||||
self.assertEqual(repr(v.as_value()), "(switch-value (sig s) (case 00 (const 1'd1)) (case 01 (const 2'd2)) (case 10 (const 2'd3)))")
|
||||
|
||||
|
||||
class SignalTestCase(FHDLTestCase):
|
||||
|
|
|
|||
|
|
@ -1623,6 +1623,69 @@ class AssignTestCase(FHDLTestCase):
|
|||
)
|
||||
""")
|
||||
|
||||
def test_switchvalue(self):
|
||||
s1 = Signal(8)
|
||||
s2 = Signal(8)
|
||||
s3 = Signal(8)
|
||||
s4 = Signal(8)
|
||||
s5 = Signal(8)
|
||||
s6 = Signal(8)
|
||||
s7 = Signal(8)
|
||||
f = Fragment()
|
||||
f.add_statements("comb", [
|
||||
SwitchValue(s5[:4], [
|
||||
(1, s1),
|
||||
((2, 3), s2),
|
||||
((), s3),
|
||||
('11--', s4),
|
||||
]).eq(s6),
|
||||
SwitchValue(s5[4:], [
|
||||
(4, s1),
|
||||
(5, s2),
|
||||
(6, s3),
|
||||
(None, s4),
|
||||
]).eq(s7),
|
||||
])
|
||||
f.add_driver(s1, "comb")
|
||||
f.add_driver(s2, "comb")
|
||||
f.add_driver(s3, "comb")
|
||||
f.add_driver(s4, "comb")
|
||||
nl = build_netlist(f, ports=[s1, s2, s3, s4, s5, s6, s7])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 's5' 0.2:10)
|
||||
(input 's6' 0.10:18)
|
||||
(input 's7' 0.18:26)
|
||||
(output 's1' 9.0:8)
|
||||
(output 's2' 10.0:8)
|
||||
(output 's3' 12.0:8)
|
||||
(output 's4' 11.0:8)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(input 's5' 2:10)
|
||||
(input 's6' 10:18)
|
||||
(input 's7' 18:26)
|
||||
(output 's1' 9.0:8)
|
||||
(output 's2' 10.0:8)
|
||||
(output 's3' 12.0:8)
|
||||
(output 's4' 11.0:8)
|
||||
))
|
||||
(cell 1 0 (matches 0.2:6 0001))
|
||||
(cell 2 0 (matches 0.2:6 0010 0011))
|
||||
(cell 3 0 (matches 0.2:6 11--))
|
||||
(cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
|
||||
(cell 5 0 (matches 0.6:10 0100))
|
||||
(cell 6 0 (matches 0.6:10 0101))
|
||||
(cell 7 0 (matches 0.6:10 0110))
|
||||
(cell 8 0 (priority_match 1 (cat 5.0 6.0 7.0 1'd1)))
|
||||
(cell 9 0 (assignment_list 8'd0 (4.0 0:8 0.10:18) (8.0 0:8 0.18:26)))
|
||||
(cell 10 0 (assignment_list 8'd0 (4.1 0:8 0.10:18) (8.1 0:8 0.18:26)))
|
||||
(cell 11 0 (assignment_list 8'd0 (4.2 0:8 0.10:18) (8.3 0:8 0.18:26)))
|
||||
(cell 12 0 (assignment_list 8'd0 (8.2 0:8 0.18:26)))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_sliced_slice(self):
|
||||
s1 = Signal(12)
|
||||
s2 = Signal(4)
|
||||
|
|
@ -2953,7 +3016,7 @@ class RhsTestCase(FHDLTestCase):
|
|||
(cell 2 0 (matches 0.50:54 0001))
|
||||
(cell 3 0 (matches 0.50:54 0010))
|
||||
(cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
|
||||
(cell 5 0 (assignment_list 0.2:10
|
||||
(cell 5 0 (assignment_list 8'd0
|
||||
(4.0 0:8 0.2:10)
|
||||
(4.1 0:8 0.10:18)
|
||||
(4.2 0:8 0.18:26)
|
||||
|
|
@ -2962,7 +3025,7 @@ class RhsTestCase(FHDLTestCase):
|
|||
(cell 7 0 (matches 0.50:54 0001))
|
||||
(cell 8 0 (matches 0.50:54 0010))
|
||||
(cell 9 0 (priority_match 1 (cat 6.0 7.0 8.0)))
|
||||
(cell 10 0 (assignment_list (cat 0.2:10 1'd0)
|
||||
(cell 10 0 (assignment_list 9'd0
|
||||
(9.0 0:9 (cat 0.2:10 1'd0))
|
||||
(9.1 0:9 (cat 0.10:18 1'd0))
|
||||
(9.2 0:9 (cat 0.42:50 0.49))
|
||||
|
|
@ -2971,7 +3034,7 @@ class RhsTestCase(FHDLTestCase):
|
|||
(cell 12 0 (matches 0.50:54 0001))
|
||||
(cell 13 0 (matches 0.50:54 0010))
|
||||
(cell 14 0 (priority_match 1 (cat 11.0 12.0 13.0)))
|
||||
(cell 15 0 (assignment_list 0.26:34
|
||||
(cell 15 0 (assignment_list 8'd0
|
||||
(14.0 0:8 0.26:34)
|
||||
(14.1 0:8 0.34:42)
|
||||
(14.2 0:8 0.42:50)
|
||||
|
|
@ -2980,7 +3043,7 @@ class RhsTestCase(FHDLTestCase):
|
|||
(cell 17 0 (matches 0.50:54 0001))
|
||||
(cell 18 0 (matches 0.50:54 0010))
|
||||
(cell 19 0 (priority_match 1 (cat 16.0 17.0 18.0)))
|
||||
(cell 20 0 (assignment_list 0.26:34
|
||||
(cell 20 0 (assignment_list 8'd0
|
||||
(19.0 0:8 0.26:34)
|
||||
(19.1 0:8 0.34:42)
|
||||
(19.2 0:8 (cat 0.50:54 4'd0))
|
||||
|
|
@ -2988,6 +3051,67 @@ class RhsTestCase(FHDLTestCase):
|
|||
)
|
||||
""")
|
||||
|
||||
def test_switchvalue(self):
|
||||
i8ua = Signal(8)
|
||||
i8ub = Signal(8)
|
||||
i8uc = Signal(8)
|
||||
i8ud = Signal(8)
|
||||
i4 = Signal(4)
|
||||
o1 = Signal(10)
|
||||
o2 = Signal(10)
|
||||
m = Module()
|
||||
m.d.comb += o1.eq(SwitchValue(i4, [
|
||||
(1, i8ua),
|
||||
((2, 3), i8ub),
|
||||
('11--', i8uc),
|
||||
]))
|
||||
m.d.comb += o2.eq(SwitchValue(i4, [
|
||||
((4, 5), i8ua),
|
||||
((), i8ub),
|
||||
((6, 7), i8uc),
|
||||
(None, i8ud),
|
||||
]))
|
||||
nl = build_netlist(Fragment.get(m, None), [i8ua, i8ub, i8uc, i8ud, i4, o1, o2])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 'i8ua' 0.2:10)
|
||||
(input 'i8ub' 0.10:18)
|
||||
(input 'i8uc' 0.18:26)
|
||||
(input 'i8ud' 0.26:34)
|
||||
(input 'i4' 0.34:38)
|
||||
(output 'o1' (cat 5.0:8 2'd0))
|
||||
(output 'o2' (cat 9.0:8 2'd0))
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(input 'i8ua' 2:10)
|
||||
(input 'i8ub' 10:18)
|
||||
(input 'i8uc' 18:26)
|
||||
(input 'i8ud' 26:34)
|
||||
(input 'i4' 34:38)
|
||||
(output 'o1' (cat 5.0:8 2'd0))
|
||||
(output 'o2' (cat 9.0:8 2'd0))
|
||||
))
|
||||
(cell 1 0 (matches 0.34:38 0001))
|
||||
(cell 2 0 (matches 0.34:38 0010 0011))
|
||||
(cell 3 0 (matches 0.34:38 11--))
|
||||
(cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
|
||||
(cell 5 0 (assignment_list 8'd0
|
||||
(4.0 0:8 0.2:10)
|
||||
(4.1 0:8 0.10:18)
|
||||
(4.2 0:8 0.18:26)
|
||||
))
|
||||
(cell 6 0 (matches 0.34:38 0100 0101))
|
||||
(cell 7 0 (matches 0.34:38 0110 0111))
|
||||
(cell 8 0 (priority_match 1 (cat 6.0 7.0 1'd1)))
|
||||
(cell 9 0 (assignment_list 8'd0
|
||||
(8.0 0:8 0.2:10)
|
||||
(8.1 0:8 0.18:26)
|
||||
(8.2 0:8 0.26:34)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
||||
def test_anyvalue(self):
|
||||
o1 = Signal(12)
|
||||
o2 = Signal(12)
|
||||
|
|
|
|||
|
|
@ -314,8 +314,8 @@ class SimulatorUnitTestCase(FHDLTestCase):
|
|||
def test_array_oob(self):
|
||||
array = Array([1, 4, 10])
|
||||
stmt = lambda y, a: y.eq(array[a])
|
||||
self.assertStatement(stmt, [C(3)], C(10))
|
||||
self.assertStatement(stmt, [C(4)], C(10))
|
||||
self.assertStatement(stmt, [C(3)], C(0))
|
||||
self.assertStatement(stmt, [C(4)], C(0))
|
||||
|
||||
def test_array_lhs(self):
|
||||
l = Signal(3, init=1)
|
||||
|
|
@ -333,8 +333,8 @@ class SimulatorUnitTestCase(FHDLTestCase):
|
|||
n = Signal(3)
|
||||
array = Array([l, m, n])
|
||||
stmt = lambda y, a, b: [array[a].eq(b), y.eq(Cat(*array))]
|
||||
self.assertStatement(stmt, [C(3), C(0b001)], C(0b001000000))
|
||||
self.assertStatement(stmt, [C(4), C(0b010)], C(0b010000000))
|
||||
self.assertStatement(stmt, [C(3), C(0b001)], C(0))
|
||||
self.assertStatement(stmt, [C(4), C(0b010)], C(0))
|
||||
|
||||
def test_array_index(self):
|
||||
array = Array(Array(x * y for y in range(10)) for x in range(10))
|
||||
|
|
@ -513,6 +513,8 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
with self.m.Switch(self.s):
|
||||
with self.m.Case(0):
|
||||
self.m.d.sync += self.o.eq(self.a + self.b)
|
||||
with self.m.Case():
|
||||
self.m.d.sync += self.o.eq(self.a * self.b)
|
||||
with self.m.Case(1):
|
||||
self.m.d.sync += self.o.eq(self.a - self.b)
|
||||
with self.m.Default():
|
||||
|
|
|
|||
Loading…
Reference in a new issue