Wanda
Catherine
parent
81c35a5922
commit
2d59242bf7
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@ -1,4 +1,5 @@
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from typing import Iterable
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from contextlib import contextmanager
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import io
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from ..utils import bits_for
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@ -47,89 +48,141 @@ def _const(value):
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assert False, f"Invalid constant {value!r}"
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class _Namer:
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def _src(src_loc):
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if src_loc is None:
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return None
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file, line = src_loc
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return f"{file}:{line}"
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class Emitter:
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def __init__(self):
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super().__init__()
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self._anon = 0
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self._index = 0
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self._names = set()
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self._indent = ""
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self._lines = []
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self.port_id = 0
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def anonymous(self):
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name = f"U$${self._anon}"
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assert name not in self._names
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self._anon += 1
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return name
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def __call__(self, line=None):
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if line is not None:
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self._lines.append(f"{self._indent}{line}\n")
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else:
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self._lines.append("\n")
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def _make_name(self, name, local):
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if name is None:
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self._index += 1
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name = f"${self._index}"
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elif not local and name[0] not in "\\$":
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name = f"\\{name}"
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while name in self._names:
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self._index += 1
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name = f"{name}${self._index}"
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self._names.add(name)
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return name
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class _BufferedBuilder:
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def __init__(self):
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super().__init__()
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self._buffer = io.StringIO()
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@contextmanager
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def indent(self):
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orig = self._indent
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self._indent += " "
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yield
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self._indent = orig
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def __str__(self):
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return self._buffer.getvalue()
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def _append(self, fmt, *args, **kwargs):
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self._buffer.write(fmt.format(*args, **kwargs))
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return "".join(self._lines)
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class _AttrBuilder:
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def __init__(self, emit_src, *args, **kwargs):
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super().__init__(*args, **kwargs)
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class Design:
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def __init__(self, emit_src=True):
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self.modules = {}
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self.emit_src = emit_src
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def _attribute(self, name, value, *, indent=0):
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self._append("{}attribute \\{} {}\n",
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" " * indent, name, _const(value))
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def module(self, name, **kwargs):
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assert name not in self.modules
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self.modules[name] = res = Module(name, emit_src=self.emit_src, **kwargs)
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return res
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def _attributes(self, attrs, *, src=None, **kwargs):
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for name, value in attrs.items():
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self._attribute(name, value, **kwargs)
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if src and self.emit_src:
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self._attribute("src", src, **kwargs)
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def __str__(self):
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emitter = Emitter()
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for module in self.modules.values():
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module.emit(emitter)
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return str(emitter)
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class _Builder(_BufferedBuilder, _Namer):
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def __init__(self, emit_src):
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super().__init__()
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class Module:
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def __init__(self, name, src_loc=None, attrs=None, emit_src=True):
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self.name = name
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self._auto_index = 0
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self.contents = {}
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self.connections = []
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self.attributes = {"generator": "Amaranth"}
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self.emit_src = emit_src
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if src_loc is not None and emit_src:
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self.attributes["src"] = _src(src_loc)
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if attrs is not None:
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self.attributes.update(attrs)
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def module(self, name=None, attrs={}, *, src=None):
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name = self._make_name(name, local=False)
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return _ModuleBuilder(self, name, attrs, src=src)
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def _auto_name(self):
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self._auto_index += 1
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return f"${self._auto_index}"
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def _name(self, name):
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if name is None:
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name = self._auto_name()
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else:
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name = f"\\{name}"
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assert name not in self.contents
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return name
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def wire(self, width, *, name=None, **kwargs):
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name = self._name(name)
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if not self.emit_src and "src_loc" in kwargs:
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del kwargs["src_loc"]
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self.contents[name] = res = Wire(width, name=name, **kwargs)
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return res
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def cell(self, kind, name=None, **kwargs):
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name = self._name(name)
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if not self.emit_src and "src_loc" in kwargs:
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del kwargs["src_loc"]
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self.contents[name] = res = Cell(kind, name=name, **kwargs)
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return res
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def memory(self, width, depth, name=None, **kwargs):
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name = self._name(name)
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if not self.emit_src and "src_loc" in kwargs:
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del kwargs["src_loc"]
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self.contents[name] = res = Memory(width, depth, name=name, **kwargs)
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return res
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def process(self, *, name=None, **kwargs):
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name = self._name(name)
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if not self.emit_src and "src_loc" in kwargs:
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del kwargs["src_loc"]
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self.contents[name] = res = Process(name=name, **kwargs)
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return res
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def connect(self, lhs, rhs):
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self.connections.append((lhs, rhs))
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def attribute(self, name, value):
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assert name not in self.attributes
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self.attributes[name] = value
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def emit(self, line):
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line.port_id = 0
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for name, value in self.attributes.items():
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line(f"attribute \\{name} {_const(value)}")
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line(f"module \\{self.name}")
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line()
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with line.indent():
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for item in self.contents.values():
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item.emit(line)
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for (lhs, rhs) in self.connections:
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line(f"connect {lhs} {rhs}")
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if self.connections:
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line()
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line("end")
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line()
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class _ModuleBuilder(_AttrBuilder, _BufferedBuilder, _Namer):
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def __init__(self, rtlil, name, attrs, *, src=None):
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super().__init__(emit_src=rtlil.emit_src)
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self.rtlil = rtlil
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self.name = name
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self.src = src
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self.attrs = {"generator": "Amaranth"}
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self.attrs.update(attrs)
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def _make_attributes(attrs, src_loc):
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res = {}
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if src_loc is not None:
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res["src"] = _src(src_loc)
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if attrs is not None:
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res.update(attrs)
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return res
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def __enter__(self):
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self._attributes(self.attrs, src=self.src)
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self._append("module {}\n", self.name)
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return self
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def __exit__(self, *args):
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self._append("end\n")
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self.rtlil._buffer.write(str(self))
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def wire(self, width, port_id=None, port_kind=None, name=None, attrs={}, src="", signed=False):
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class Wire:
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def __init__(self, width, *, name, src_loc=None, attrs=None, signed=False, port_kind=None):
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# Very large wires are unlikely to work. Verilog 1364-2005 requires the limit on vectors
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# to be at least 2**16 bits, and Yosys 0.9 cannot read RTLIL with wires larger than 2**32
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# bits. In practice, wires larger than 2**16 bits, although accepted, cause performance
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@ -137,131 +190,192 @@ class _ModuleBuilder(_AttrBuilder, _BufferedBuilder, _Namer):
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if width > 2 ** 16:
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raise OverflowError("Wire created at {} is {} bits wide, which is unlikely to "
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"synthesize correctly"
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.format(src or "unknown location", width))
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.format(_src(src_loc) or "unknown location", width))
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self.name = name
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self.width = width
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self.signed = signed
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self.port_kind = port_kind
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self.attributes = _make_attributes(attrs, src_loc)
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self._attributes(attrs, src=src, indent=1)
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name = self._make_name(name, local=False)
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signed = " signed" if signed else ""
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if port_id is None:
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self._append(" wire width {}{} {}\n", width, signed, name)
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def attribute(self, name, value):
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assert name not in self.attributes
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self.attributes[name] = value
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def emit(self, line):
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for name, value in self.attributes.items():
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line(f"attribute \\{name} {_const(value)}")
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signed = " signed" if self.signed else ""
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if self.port_kind is None:
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line(f"wire width {self.width}{signed} {self.name}")
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else:
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assert port_kind in ("input", "output", "inout")
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# By convention, Yosys ports named $\d+ are positional, so there is no way to use
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# a port with such a name. See amaranth-lang/amaranth#733.
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assert port_id is not None
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self._append(" wire width {} {} {}{} {}\n", width, port_kind, port_id, signed, name)
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return name
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def connect(self, lhs, rhs):
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self._append(" connect {} {}\n", lhs, rhs)
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def memory(self, width, size, name=None, attrs={}, src=""):
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self._attributes(attrs, src=src, indent=1)
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name = self._make_name(name, local=False)
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self._append(" memory width {} size {} {}\n", width, size, name)
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return name
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def cell(self, kind, name=None, params={}, ports={}, attrs={}, src=""):
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self._attributes(attrs, src=src, indent=1)
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name = self._make_name(name, local=False)
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self._append(" cell {} {}\n", kind, name)
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for param, value in params.items():
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if isinstance(value, float):
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self._append(" parameter real \\{} \"{!r}\"\n",
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param, value)
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elif _signed(value):
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self._append(" parameter signed \\{} {}\n",
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param, _const(value))
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else:
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self._append(" parameter \\{} {}\n",
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param, _const(value))
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for port, wire in ports.items():
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self._append(" connect \\{} {}\n", port, wire)
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self._append(" end\n")
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return name
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def process(self, name=None, attrs={}, src=""):
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name = self._make_name(name, local=True)
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return _ProcessBuilder(self, name, attrs, src)
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line(f"wire width {self.width} {self.port_kind} {line.port_id} {signed} {self.name}")
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line.port_id += 1
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line()
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class _ProcessBuilder(_AttrBuilder, _BufferedBuilder):
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def __init__(self, rtlil, name, attrs, src):
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super().__init__(emit_src=rtlil.emit_src)
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self.rtlil = rtlil
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self.name = name
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self.attrs = {}
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self.src = src
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class Cell:
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def __init__(self, kind, *, name, ports=None, parameters=None, attrs=None, src_loc=None):
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self.kind = kind
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self.name = name
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self.parameters = parameters or {}
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self.ports = ports or {}
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self.attributes = _make_attributes(attrs, src_loc)
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def __enter__(self):
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self._attributes(self.attrs, src=self.src, indent=1)
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self._append(" process {}\n", self.name)
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return self
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def port(self, name, value):
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assert name not in self.ports
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self.ports[name] = value
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def __exit__(self, *args):
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self._append(" end\n")
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self.rtlil._buffer.write(str(self))
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def parameter(self, name, value):
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assert name not in self.parameters
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self.parameters[name] = value
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def case(self):
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return _CaseBuilder(self, indent=2)
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def attribute(self, name, value):
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assert name not in self.attributes
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self.attributes[name] = value
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def emit(self, line):
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for name, value in self.attributes.items():
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line(f"attribute \\{name} {_const(value)}")
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line(f"cell {self.kind} {self.name}")
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with line.indent():
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for name, value in self.parameters.items():
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if isinstance(value, float):
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line(f"parameter real \\{name} \"{value!r}\"")
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elif _signed(value):
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line(f"parameter signed \\{name} {_const(value)}")
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else:
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line(f"parameter \\{name} {_const(value)}")
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for name, value in self.ports.items():
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line(f"connect \\{name} {value}")
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line(f"end")
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line()
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class _CaseBuilder:
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def __init__(self, rtlil, indent):
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self.rtlil = rtlil
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self.indent = indent
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class Memory:
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def __init__(self, width, depth, *, name, attrs=None, src_loc=None):
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self.width = width
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self.depth = depth
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self.name = name
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self.attributes = _make_attributes(attrs, src_loc)
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def _append(self, *args, **kwargs):
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self.rtlil._append(*args, **kwargs)
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def attribute(self, name, value):
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assert name not in self.attributes
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self.attributes[name] = value
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def __enter__(self):
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return self
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def emit(self, line):
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for name, value in self.attributes.items():
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line(f"attribute \\{name} {_const(value)}")
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line(f"memory width {self.width} size {self.depth} {self.name}")
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line()
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def __exit__(self, *args):
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pass
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def _emit_process_contents(contents, emit):
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index = 0
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while index < len(contents) and isinstance(contents[index], Assignment):
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contents[index].emit(emit)
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index += 1
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while index < len(contents):
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if isinstance(contents[index], Assignment):
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emit(f"switch {{}}")
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with emit.indent():
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emit(f"case")
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with emit.indent():
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while index < len(contents) and isinstance(contents[index], Assignment):
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contents[index].emit(emit)
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index += 1
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emit(f"end")
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else:
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contents[index].emit(emit)
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index += 1
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class Process:
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def __init__(self, *, name, attrs=None, src_loc=None):
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self.name = name
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self.contents = []
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self.attributes = _make_attributes(attrs, src_loc)
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def attribute(self, name, value):
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assert name not in self.attributes
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self.attributes[name] = value
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def assign(self, lhs, rhs):
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self._append("{}assign {} {}\n", " " * self.indent, lhs, rhs)
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self.contents.append(Assignment(lhs, rhs))
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def switch(self, cond, attrs={}, src=""):
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return _SwitchBuilder(self.rtlil, cond, attrs, src, self.indent)
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def switch(self, sel):
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res = Switch(sel)
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self.contents.append(res)
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return res
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def emit(self, line):
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for name, value in self.attributes.items():
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line(f"attribute \\{name} {_const(value)}")
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line(f"process {self.name}")
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with line.indent():
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_emit_process_contents(self.contents, line)
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line(f"end")
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line()
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class _SwitchBuilder(_AttrBuilder):
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def __init__(self, rtlil, cond, attrs, src, indent):
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super().__init__(emit_src=rtlil.emit_src)
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self.rtlil = rtlil
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self.cond = cond
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self.attrs = attrs
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self.src = src
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self.indent = indent
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class Assignment:
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def __init__(self, lhs, rhs):
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self.lhs = lhs
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self.rhs = rhs
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def _append(self, *args, **kwargs):
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self.rtlil._append(*args, **kwargs)
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def emit(self, line):
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line(f"assign {self.lhs} {self.rhs}")
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def __enter__(self):
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self._attributes(self.attrs, src=self.src, indent=self.indent)
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self._append("{}switch {}\n", " " * self.indent, self.cond)
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return self
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def __exit__(self, *args):
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self._append("{}end\n", " " * self.indent)
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class Switch:
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def __init__(self, sel):
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self.sel = sel
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self.cases = []
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def case(self, *values, attrs={}, src=""):
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self._attributes(attrs, src=src, indent=self.indent + 1)
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if values == ():
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self._append("{}case\n", " " * (self.indent + 1))
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def case(self, patterns):
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res = Case(patterns)
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if patterns:
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# RTLIL doesn't support cases with empty pattern list (they get interpreted
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# as a default case instead, which is batshit and the exact opposite of
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# what we want). When such a case is requested, return a case so that
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# the caller can emit stuff into it, but don't actually include it in
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# the switch.
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self.cases.append(res)
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return res
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def default(self):
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res = Case(())
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self.cases.append(res)
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return res
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def emit(self, line):
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line(f"switch {self.sel}")
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with line.indent():
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for case in self.cases:
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case.emit(line)
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line("end")
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class Case:
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def __init__(self, patterns):
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self.patterns = patterns
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self.contents = []
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|
||||
def assign(self, lhs, rhs):
|
||||
self.contents.append(Assignment(lhs, rhs))
|
||||
|
||||
def switch(self, sel):
|
||||
res = Switch(sel)
|
||||
self.contents.append(res)
|
||||
return res
|
||||
|
||||
def emit(self, line):
|
||||
if self.patterns:
|
||||
patterns = ", ".join(f"{len(pattern)}'{pattern}" for pattern in self.patterns)
|
||||
line(f"case {patterns}")
|
||||
else:
|
||||
self._append("{}case {}\n", " " * (self.indent + 1),
|
||||
", ".join(f"{len(value)}'{value}" for value in values))
|
||||
return _CaseBuilder(self.rtlil, self.indent + 2)
|
||||
|
||||
|
||||
def _src(src_loc):
|
||||
if src_loc is None:
|
||||
return None
|
||||
file, line = src_loc
|
||||
return f"{file}:{line}"
|
||||
line(f"case")
|
||||
with line.indent():
|
||||
_emit_process_contents(self.contents, line)
|
||||
|
||||
|
||||
class MemoryInfo:
|
||||
|
|
@ -316,7 +430,7 @@ class ModuleEmitter:
|
|||
if isinstance(cell, _nir.Memory):
|
||||
self.memories[cell_idx] = MemoryInfo(
|
||||
self.builder.memory(cell.width, cell.depth, name=cell.name,
|
||||
attrs=cell.attributes, src=_src(cell.src_loc)))
|
||||
attrs=cell.attributes, src_loc=cell.src_loc).name)
|
||||
|
||||
for cell_idx in self.module.cells:
|
||||
cell = self.netlist.cells[cell_idx]
|
||||
|
|
@ -392,9 +506,9 @@ class ModuleEmitter:
|
|||
shape = signal.shape()
|
||||
wire = self.builder.wire(width=shape.width, signed=shape.signed,
|
||||
name=name, attrs=attrs,
|
||||
src=_src(signal.src_loc))
|
||||
src_loc=signal.src_loc)
|
||||
self.sigport_wires[name] = (wire, value)
|
||||
self.name_map[signal] = (*self.module.name, wire[1:])
|
||||
self.name_map[signal] = (*self.module.name, wire.name[1:])
|
||||
|
||||
def emit_port_wires(self):
|
||||
named_signals = {name: signal for signal, name in self.module.signal_names.items()}
|
||||
|
|
@ -403,9 +517,9 @@ class ModuleEmitter:
|
|||
if name in named_signals:
|
||||
signed = named_signals[name].shape().signed
|
||||
wire = self.builder.wire(width=len(value), signed=signed,
|
||||
port_id=port_id, port_kind=flow.value,
|
||||
port_kind=flow.value,
|
||||
name=name, attrs=self.value_attrs.get(value, {}),
|
||||
src=_src(self.value_src_loc.get(value)))
|
||||
src_loc=self.value_src_loc.get(value))
|
||||
self.sigport_wires[name] = (wire, value)
|
||||
if flow == _nir.ModuleNetFlow.Output:
|
||||
continue
|
||||
|
|
@ -425,9 +539,9 @@ class ModuleEmitter:
|
|||
attrs = {}
|
||||
src_loc = None
|
||||
wire = self.builder.wire(width=len(value),
|
||||
port_id=port_id, port_kind=dir.value,
|
||||
port_kind=dir.value,
|
||||
name=name, attrs=attrs,
|
||||
src=_src(src_loc))
|
||||
src_loc=src_loc)
|
||||
for bit, net in enumerate(value):
|
||||
self.ionets[net] = (wire, bit)
|
||||
|
||||
|
|
@ -516,9 +630,9 @@ class ModuleEmitter:
|
|||
bit += 1
|
||||
width = end_pos - begin_pos
|
||||
if width == 1:
|
||||
chunks.append(f"{wire} [{start_bit}]")
|
||||
chunks.append(f"{wire.name} [{start_bit}]")
|
||||
else:
|
||||
chunks.append(f"{wire} [{start_bit + width - 1}:{start_bit}]")
|
||||
chunks.append(f"{wire.name} [{start_bit + width - 1}:{start_bit}]")
|
||||
begin_pos = end_pos
|
||||
|
||||
if len(chunks) == 1:
|
||||
|
|
@ -538,9 +652,9 @@ class ModuleEmitter:
|
|||
bit += 1
|
||||
width = end_pos - begin_pos
|
||||
if width == 1:
|
||||
chunks.append(f"{wire} [{start_bit}]")
|
||||
chunks.append(f"{wire.name} [{start_bit}]")
|
||||
else:
|
||||
chunks.append(f"{wire} [{start_bit + width - 1}:{start_bit}]")
|
||||
chunks.append(f"{wire.name} [{start_bit + width - 1}:{start_bit}]")
|
||||
begin_pos = end_pos
|
||||
|
||||
if len(chunks) == 1:
|
||||
|
|
@ -550,7 +664,7 @@ class ModuleEmitter:
|
|||
def emit_connects(self):
|
||||
for name, (wire, value) in self.sigport_wires.items():
|
||||
if name not in self.driven_sigports:
|
||||
self.builder.connect(wire, self.sigspec(value))
|
||||
self.builder.connect(wire.name, self.sigspec(value))
|
||||
|
||||
def emit_submodules(self):
|
||||
for submodule_idx in self.module.submodules:
|
||||
|
|
@ -563,7 +677,7 @@ class ModuleEmitter:
|
|||
for name, (value, _dir) in submodule.io_ports.items():
|
||||
ports[name] = self.io_sigspec(value)
|
||||
self.builder.cell(f"\\{dotted_name}", submodule.name[-1], ports=ports,
|
||||
src=_src(submodule.cell_src_loc))
|
||||
src_loc=submodule.cell_src_loc)
|
||||
|
||||
def emit_assignment_list(self, cell_idx, cell):
|
||||
def emit_assignments(case, cond):
|
||||
|
|
@ -573,30 +687,13 @@ class ModuleEmitter:
|
|||
# letting parent invocation take care of the remaining assignments.
|
||||
nonlocal pos
|
||||
|
||||
emitted_switch = False
|
||||
while pos < len(cell.assignments):
|
||||
assign = cell.assignments[pos]
|
||||
if assign.cond == cond and not emitted_switch:
|
||||
# Not nested, and we didn't emit a switch yet, so emit the assignment.
|
||||
if assign.cond == cond:
|
||||
# Not nested, so emit the assignment.
|
||||
case.assign(self.sigspec(lhs[assign.start:assign.start + len(assign.value)]),
|
||||
self.sigspec(assign.value))
|
||||
pos += 1
|
||||
elif assign.cond == cond:
|
||||
# Not nested, but we emitted a subswitch. Wrap the assignments in a dummy
|
||||
# switch. This is necessary because Yosys executes all assignments before all
|
||||
# subswitches (but allows you to mix asssignments and switches in RTLIL, for
|
||||
# maximum confusion).
|
||||
with case.switch("{ }") as switch:
|
||||
with switch.case("") as subcase:
|
||||
while pos < len(cell.assignments):
|
||||
assign = cell.assignments[pos]
|
||||
if assign.cond == cond:
|
||||
subcase.assign(self.sigspec(lhs[assign.start:assign.start +
|
||||
len(assign.value)]),
|
||||
self.sigspec(assign.value))
|
||||
pos += 1
|
||||
else:
|
||||
break
|
||||
else:
|
||||
# Condition doesn't match this case's condition — either we encountered
|
||||
# a nested condition, or we should break out. Try to find out exactly
|
||||
|
|
@ -627,31 +724,25 @@ class ModuleEmitter:
|
|||
break
|
||||
# Now emit cases for all PriorityMatch inputs, in sequence. Consume as many
|
||||
# assignments as possible along the way.
|
||||
with case.switch(self.sigspec(test)) as switch:
|
||||
for bit, net in enumerate(priority_cell.inputs):
|
||||
subcond = _nir.Net.from_cell(priority_cell_idx, bit)
|
||||
if net == _nir.Net.from_const(1):
|
||||
patterns = ()
|
||||
else:
|
||||
# Validate the above assumptions.
|
||||
matches_cell = self.netlist.cells[net.cell]
|
||||
assert isinstance(matches_cell, _nir.Matches)
|
||||
assert test == matches_cell.value
|
||||
patterns = matches_cell.patterns
|
||||
# RTLIL cannot support empty pattern sets.
|
||||
assert patterns
|
||||
with switch.case(*patterns) as subcase:
|
||||
emit_assignments(subcase, subcond)
|
||||
emitted_switch = True
|
||||
switch = case.switch(self.sigspec(test))
|
||||
for bit, net in enumerate(priority_cell.inputs):
|
||||
subcond = _nir.Net.from_cell(priority_cell_idx, bit)
|
||||
if net == _nir.Net.from_const(1):
|
||||
emit_assignments(switch.default(), subcond)
|
||||
else:
|
||||
# Validate the above assumptions.
|
||||
matches_cell = self.netlist.cells[net.cell]
|
||||
assert isinstance(matches_cell, _nir.Matches)
|
||||
assert test == matches_cell.value
|
||||
patterns = matches_cell.patterns
|
||||
emit_assignments(switch.case(patterns), subcond)
|
||||
|
||||
lhs = _nir.Value(_nir.Net.from_cell(cell_idx, bit) for bit in range(len(cell.default)))
|
||||
with self.builder.process(src=_src(cell.src_loc)) as proc:
|
||||
with proc.case() as root_case:
|
||||
root_case.assign(self.sigspec(lhs), self.sigspec(cell.default))
|
||||
|
||||
pos = 0 # nonlocally used in `emit_assignments`
|
||||
emit_assignments(root_case, _nir.Net.from_const(1))
|
||||
assert pos == len(cell.assignments)
|
||||
proc = self.builder.process(src_loc=cell.src_loc)
|
||||
proc.assign(self.sigspec(lhs), self.sigspec(cell.default))
|
||||
pos = 0 # nonlocally used in `emit_assignments`
|
||||
emit_assignments(proc, _nir.Net.from_const(1))
|
||||
assert pos == len(cell.assignments)
|
||||
|
||||
def emit_operator(self, cell_idx, cell):
|
||||
UNARY_OPERATORS = {
|
||||
|
|
@ -693,12 +784,12 @@ class ModuleEmitter:
|
|||
operand, = cell.inputs
|
||||
self.builder.cell(cell_type, ports={
|
||||
"A": self.sigspec(operand),
|
||||
"Y": self.cell_wires[cell_idx]
|
||||
}, params={
|
||||
"Y": self.cell_wires[cell_idx].name
|
||||
}, parameters={
|
||||
"A_SIGNED": False,
|
||||
"A_WIDTH": len(operand),
|
||||
"Y_WIDTH": cell.width,
|
||||
}, src=_src(cell.src_loc))
|
||||
}, src_loc=cell.src_loc)
|
||||
elif len(cell.inputs) == 2:
|
||||
cell_type, a_signed, b_signed = BINARY_OPERATORS[cell.operator]
|
||||
operand_a, operand_b = cell.inputs
|
||||
|
|
@ -707,43 +798,43 @@ class ModuleEmitter:
|
|||
self.builder.cell(cell_type, ports={
|
||||
"A": self.sigspec(operand_a),
|
||||
"B": self.sigspec(operand_b),
|
||||
"Y": result,
|
||||
}, params={
|
||||
"Y": result.name,
|
||||
}, parameters={
|
||||
"A_SIGNED": a_signed,
|
||||
"B_SIGNED": b_signed,
|
||||
"A_WIDTH": len(operand_a),
|
||||
"B_WIDTH": len(operand_b),
|
||||
"Y_WIDTH": cell.width,
|
||||
}, src=_src(cell.src_loc))
|
||||
}, src_loc=cell.src_loc)
|
||||
nonzero = self.builder.wire(1)
|
||||
self.builder.cell("$reduce_bool", ports={
|
||||
"A": self.sigspec(operand_b),
|
||||
"Y": nonzero,
|
||||
}, params={
|
||||
"Y": nonzero.name,
|
||||
}, parameters={
|
||||
"A_SIGNED": False,
|
||||
"A_WIDTH": len(operand_b),
|
||||
"Y_WIDTH": 1,
|
||||
}, src=_src(cell.src_loc))
|
||||
}, src_loc=cell.src_loc)
|
||||
self.builder.cell("$mux", ports={
|
||||
"S": nonzero,
|
||||
"S": nonzero.name,
|
||||
"A": self.sigspec(_nir.Value.zeros(cell.width)),
|
||||
"B": result,
|
||||
"Y": self.cell_wires[cell_idx]
|
||||
}, params={
|
||||
"B": result.name,
|
||||
"Y": self.cell_wires[cell_idx].name
|
||||
}, parameters={
|
||||
"WIDTH": cell.width,
|
||||
}, src=_src(cell.src_loc))
|
||||
}, src_loc=cell.src_loc)
|
||||
else:
|
||||
self.builder.cell(cell_type, ports={
|
||||
"A": self.sigspec(operand_a),
|
||||
"B": self.sigspec(operand_b),
|
||||
"Y": self.cell_wires[cell_idx],
|
||||
}, params={
|
||||
"Y": self.cell_wires[cell_idx].name,
|
||||
}, parameters={
|
||||
"A_SIGNED": a_signed,
|
||||
"B_SIGNED": b_signed,
|
||||
"A_WIDTH": len(operand_a),
|
||||
"B_WIDTH": len(operand_b),
|
||||
"Y_WIDTH": cell.width,
|
||||
}, src=_src(cell.src_loc))
|
||||
}, src_loc=cell.src_loc)
|
||||
else:
|
||||
assert cell.operator == "m"
|
||||
condition, if_true, if_false = cell.inputs
|
||||
|
|
@ -751,10 +842,10 @@ class ModuleEmitter:
|
|||
"S": self.sigspec(condition),
|
||||
"A": self.sigspec(if_false),
|
||||
"B": self.sigspec(if_true),
|
||||
"Y": self.cell_wires[cell_idx]
|
||||
}, params={
|
||||
"Y": self.cell_wires[cell_idx].name
|
||||
}, parameters={
|
||||
"WIDTH": cell.width,
|
||||
}, src=_src(cell.src_loc))
|
||||
}, src_loc=cell.src_loc)
|
||||
|
||||
def emit_part(self, cell_idx, cell):
|
||||
if cell.stride == 1:
|
||||
|
|
@ -762,38 +853,38 @@ class ModuleEmitter:
|
|||
offset_width = len(cell.offset)
|
||||
else:
|
||||
stride = _ast.Const(cell.stride)
|
||||
offset_width = len(cell.offset) + stride.width
|
||||
offset = self.builder.wire(offset_width)
|
||||
offset_width = len(cell.offset) + len(stride)
|
||||
offset = self.builder.wire(offset_width).name
|
||||
self.builder.cell("$mul", ports={
|
||||
"A": self.sigspec(cell.offset),
|
||||
"B": _const(stride),
|
||||
"Y": offset,
|
||||
}, params={
|
||||
}, parameters={
|
||||
"A_SIGNED": False,
|
||||
"B_SIGNED": False,
|
||||
"A_WIDTH": len(cell.offset),
|
||||
"B_WIDTH": stride.width,
|
||||
"B_WIDTH": len(stride),
|
||||
"Y_WIDTH": offset_width,
|
||||
}, src=_src(cell.src_loc))
|
||||
}, src_loc=cell.src_loc)
|
||||
self.builder.cell("$shift", ports={
|
||||
"A": self.sigspec(cell.value),
|
||||
"B": offset,
|
||||
"Y": self.cell_wires[cell_idx],
|
||||
}, params={
|
||||
"Y": self.cell_wires[cell_idx].name,
|
||||
}, parameters={
|
||||
"A_SIGNED": cell.value_signed,
|
||||
"B_SIGNED": False,
|
||||
"A_WIDTH": len(cell.value),
|
||||
"B_WIDTH": offset_width,
|
||||
"Y_WIDTH": cell.width,
|
||||
}, src=_src(cell.src_loc))
|
||||
}, src_loc=cell.src_loc)
|
||||
|
||||
def emit_flip_flop(self, cell_idx, cell):
|
||||
ports = {
|
||||
"D": self.sigspec(cell.data),
|
||||
"CLK": self.sigspec(cell.clk),
|
||||
"Q": self.cell_wires[cell_idx]
|
||||
"Q": self.cell_wires[cell_idx].name
|
||||
}
|
||||
params = {
|
||||
parameters = {
|
||||
"WIDTH": len(cell.data),
|
||||
"CLK_POLARITY": {
|
||||
"pos": True,
|
||||
|
|
@ -805,9 +896,9 @@ class ModuleEmitter:
|
|||
else:
|
||||
cell_type = "$adff"
|
||||
ports["ARST"] = self.sigspec(cell.arst)
|
||||
params["ARST_POLARITY"] = True
|
||||
params["ARST_VALUE"] = _ast.Const(cell.init, len(cell.data))
|
||||
self.builder.cell(cell_type, ports=ports, params=params, src=_src(cell.src_loc))
|
||||
parameters["ARST_POLARITY"] = True
|
||||
parameters["ARST_VALUE"] = _ast.Const(cell.init, len(cell.data))
|
||||
self.builder.cell(cell_type, ports=ports, parameters=parameters, src_loc=cell.src_loc)
|
||||
|
||||
def emit_io_buffer(self, cell_idx, cell):
|
||||
if cell.dir is not _nir.IODirection.Input:
|
||||
|
|
@ -818,11 +909,11 @@ class ModuleEmitter:
|
|||
"Y": self.io_sigspec(cell.port),
|
||||
"A": self.sigspec(cell.o),
|
||||
"EN": self.sigspec(cell.oe),
|
||||
}, params={
|
||||
}, parameters={
|
||||
"WIDTH": len(cell.port),
|
||||
}, src=_src(cell.src_loc))
|
||||
}, src_loc=cell.src_loc)
|
||||
if cell.dir is not _nir.IODirection.Output:
|
||||
self.builder.connect(self.cell_wires[cell_idx], self.io_sigspec(cell.port))
|
||||
self.builder.connect(self.cell_wires[cell_idx].name, self.io_sigspec(cell.port))
|
||||
|
||||
def emit_memory(self, cell_idx, cell):
|
||||
memory_info = self.memories[cell_idx]
|
||||
|
|
@ -834,13 +925,13 @@ class ModuleEmitter:
|
|||
for bit in range(cell.width)
|
||||
),
|
||||
"EN": self.sigspec(_nir.Value.ones(cell.width)),
|
||||
}, params={
|
||||
}, parameters={
|
||||
"MEMID": memory_info.memid,
|
||||
"ABITS": 0,
|
||||
"WIDTH": cell.width,
|
||||
"WORDS": cell.depth,
|
||||
"PRIORITY": 0,
|
||||
}, src=_src(cell.src_loc))
|
||||
}, src_loc=cell.src_loc)
|
||||
|
||||
def emit_write_port(self, cell_idx, cell):
|
||||
memory_info = self.memories[cell.memory]
|
||||
|
|
@ -850,7 +941,7 @@ class ModuleEmitter:
|
|||
"EN": self.sigspec(cell.en),
|
||||
"CLK": self.sigspec(cell.clk),
|
||||
}
|
||||
params = {
|
||||
parameters = {
|
||||
"MEMID": memory_info.memid,
|
||||
"ABITS": len(cell.addr),
|
||||
"WIDTH": len(cell.data),
|
||||
|
|
@ -862,13 +953,13 @@ class ModuleEmitter:
|
|||
"PORTID": memory_info.write_port_ids[cell_idx],
|
||||
"PRIORITY_MASK": 0,
|
||||
}
|
||||
self.builder.cell(f"$memwr_v2", ports=ports, params=params, src=_src(cell.src_loc))
|
||||
self.builder.cell(f"$memwr_v2", ports=ports, parameters=parameters, src_loc=cell.src_loc)
|
||||
|
||||
def emit_read_port(self, cell_idx, cell):
|
||||
memory_info = self.memories[cell.memory]
|
||||
ports = {
|
||||
"ADDR": self.sigspec(cell.addr),
|
||||
"DATA": self.cell_wires[cell_idx],
|
||||
"DATA": self.cell_wires[cell_idx].name,
|
||||
"ARST": self.sigspec(_nir.Net.from_const(0)),
|
||||
"SRST": self.sigspec(_nir.Net.from_const(0)),
|
||||
}
|
||||
|
|
@ -879,7 +970,7 @@ class ModuleEmitter:
|
|||
1 << memory_info.write_port_ids[write_port_cell_index]
|
||||
for write_port_cell_index in cell.transparent_for
|
||||
)
|
||||
params = {
|
||||
parameters = {
|
||||
"MEMID": memory_info.memid,
|
||||
"ABITS": len(cell.addr),
|
||||
"WIDTH": cell.width,
|
||||
|
|
@ -895,7 +986,7 @@ class ModuleEmitter:
|
|||
"EN": self.sigspec(_nir.Net.from_const(1)),
|
||||
"CLK": self.sigspec(_nir.Net.from_const(0)),
|
||||
})
|
||||
params.update({
|
||||
parameters.update({
|
||||
"CLK_ENABLE": False,
|
||||
"CLK_POLARITY": True,
|
||||
})
|
||||
|
|
@ -904,14 +995,14 @@ class ModuleEmitter:
|
|||
"EN": self.sigspec(cell.en),
|
||||
"CLK": self.sigspec(cell.clk),
|
||||
})
|
||||
params.update({
|
||||
parameters.update({
|
||||
"CLK_ENABLE": True,
|
||||
"CLK_POLARITY": {
|
||||
"pos": True,
|
||||
"neg": False,
|
||||
}[cell.clk_edge],
|
||||
})
|
||||
self.builder.cell(f"$memrd_v2", ports=ports, params=params, src=_src(cell.src_loc))
|
||||
self.builder.cell(f"$memrd_v2", ports=ports, parameters=parameters, src_loc=cell.src_loc)
|
||||
|
||||
def emit_print(self, cell_idx, cell):
|
||||
args = []
|
||||
|
|
@ -964,50 +1055,51 @@ class ModuleEmitter:
|
|||
"EN": self.sigspec(cell.en),
|
||||
"ARGS": self.sigspec(_nir.Value(args)),
|
||||
}
|
||||
params = {
|
||||
parameters = {
|
||||
"FORMAT": "".join(format),
|
||||
"ARGS_WIDTH": len(args),
|
||||
"PRIORITY": -cell_idx,
|
||||
}
|
||||
if isinstance(cell, (_nir.AsyncPrint, _nir.AsyncProperty)):
|
||||
ports["TRG"] = self.sigspec(_nir.Value())
|
||||
params["TRG_ENABLE"] = False
|
||||
params["TRG_WIDTH"] = 0
|
||||
params["TRG_POLARITY"] = 0
|
||||
parameters["TRG_ENABLE"] = False
|
||||
parameters["TRG_WIDTH"] = 0
|
||||
parameters["TRG_POLARITY"] = 0
|
||||
if isinstance(cell, (_nir.SyncPrint, _nir.SyncProperty)):
|
||||
ports["TRG"] = self.sigspec(cell.clk)
|
||||
params["TRG_ENABLE"] = True
|
||||
params["TRG_WIDTH"] = 1
|
||||
params["TRG_POLARITY"] = cell.clk_edge == "pos"
|
||||
parameters["TRG_ENABLE"] = True
|
||||
parameters["TRG_WIDTH"] = 1
|
||||
parameters["TRG_POLARITY"] = cell.clk_edge == "pos"
|
||||
if isinstance(cell, (_nir.AsyncPrint, _nir.SyncPrint)):
|
||||
self.builder.cell(f"$print", params=params, ports=ports, src=_src(cell.src_loc))
|
||||
self.builder.cell(f"$print", parameters=parameters, ports=ports, src_loc=cell.src_loc)
|
||||
if isinstance(cell, (_nir.AsyncProperty, _nir.SyncProperty)):
|
||||
params["FLAVOR"] = cell.kind
|
||||
parameters["FLAVOR"] = cell.kind
|
||||
ports["A"] = self.sigspec(cell.test)
|
||||
self.builder.cell(f"$check", params=params, ports=ports, src=_src(cell.src_loc))
|
||||
self.builder.cell(f"$check", parameters=parameters, ports=ports, src_loc=cell.src_loc)
|
||||
|
||||
def emit_any_value(self, cell_idx, cell):
|
||||
self.builder.cell(f"${cell.kind}", ports={
|
||||
"Y": self.cell_wires[cell_idx],
|
||||
}, params={
|
||||
"Y": self.cell_wires[cell_idx].name,
|
||||
}, parameters={
|
||||
"WIDTH": cell.width,
|
||||
}, src=_src(cell.src_loc))
|
||||
}, src_loc=cell.src_loc)
|
||||
|
||||
def emit_initial(self, cell_idx, cell):
|
||||
self.builder.cell("$initstate", ports={
|
||||
"Y": self.cell_wires[cell_idx],
|
||||
}, src=_src(cell.src_loc))
|
||||
"Y": self.cell_wires[cell_idx].name,
|
||||
}, src_loc=cell.src_loc)
|
||||
|
||||
def emit_instance(self, cell_idx, cell):
|
||||
ports = {}
|
||||
for name, nets in cell.ports_i.items():
|
||||
ports[name] = self.sigspec(nets)
|
||||
for name in cell.ports_o:
|
||||
ports[name] = self.instance_wires[cell_idx, name]
|
||||
ports[name] = self.instance_wires[cell_idx, name].name
|
||||
for name, (ionets, _dir) in cell.ports_io.items():
|
||||
ports[name] = self.io_sigspec(ionets)
|
||||
self.builder.cell(f"\\{cell.type}", cell.name, ports=ports, params=cell.parameters,
|
||||
attrs=cell.attributes, src=_src(cell.src_loc))
|
||||
self.builder.cell(f"\\{cell.type}", cell.name, ports=ports,
|
||||
parameters=cell.parameters, attrs=cell.attributes,
|
||||
src_loc=cell.src_loc)
|
||||
|
||||
def emit_cells(self):
|
||||
for cell_idx in self.module.cells:
|
||||
|
|
@ -1071,16 +1163,15 @@ def convert_fragment(fragment, ports=(), name="top", *, emit_src=True, **kwargs)
|
|||
name_map = _ast.SignalDict()
|
||||
netlist = _ir.build_netlist(fragment, ports=ports, name=name, **kwargs)
|
||||
empty_checker = EmptyModuleChecker(netlist)
|
||||
builder = _Builder(emit_src=emit_src)
|
||||
builder = Design(emit_src=emit_src)
|
||||
for module_idx, module in enumerate(netlist.modules):
|
||||
if empty_checker.is_empty(module_idx):
|
||||
continue
|
||||
attrs = {}
|
||||
module_builder = builder.module(".".join(module.name), src_loc=module.src_loc)
|
||||
if module_idx == 0:
|
||||
attrs["top"] = 1
|
||||
with builder.module(".".join(module.name), attrs=attrs, src=_src(module.src_loc)) as module_builder:
|
||||
ModuleEmitter(module_builder, netlist, module, name_map,
|
||||
empty_checker=empty_checker).emit()
|
||||
module_builder.attribute("top", 1)
|
||||
ModuleEmitter(module_builder, netlist, module, name_map,
|
||||
empty_checker=empty_checker).emit()
|
||||
return str(builder), name_map
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -928,9 +928,6 @@ class NetlistEmitter:
|
|||
elems = []
|
||||
for patterns, elem, in value.cases:
|
||||
if patterns is not None:
|
||||
if not patterns:
|
||||
# Hack: empty pattern set cannot be supported by RTLIL.
|
||||
continue
|
||||
for pattern in patterns:
|
||||
assert len(pattern) == len(test)
|
||||
cell = _nir.Matches(module_idx, value=test, patterns=patterns,
|
||||
|
|
@ -1069,9 +1066,6 @@ class NetlistEmitter:
|
|||
elems = []
|
||||
for patterns, elem in lhs.cases:
|
||||
if patterns is not None:
|
||||
if not patterns:
|
||||
# Hack: empty pattern set cannot be supported by RTLIL.
|
||||
continue
|
||||
for pattern in patterns:
|
||||
assert len(pattern) == len(test)
|
||||
cell = _nir.Matches(module_idx, value=test, patterns=patterns,
|
||||
|
|
@ -1169,9 +1163,6 @@ class NetlistEmitter:
|
|||
case_stmts = []
|
||||
for patterns, stmts, case_src_loc in stmt.cases:
|
||||
if patterns is not None:
|
||||
if not patterns:
|
||||
# Hack: empty pattern set cannot be supported by RTLIL.
|
||||
continue
|
||||
for pattern in patterns:
|
||||
assert len(pattern) == len(test)
|
||||
cell = _nir.Matches(module_idx, value=test, patterns=patterns,
|
||||
|
|
|
|||
1834
tests/test_back_rtlil.py
Normal file
1834
tests/test_back_rtlil.py
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -1632,32 +1632,33 @@ class AssignTestCase(FHDLTestCase):
|
|||
(input 's5' 0.2:10)
|
||||
(input 's6' 0.10:18)
|
||||
(input 's7' 0.18:26)
|
||||
(output 's1' 9.0:8)
|
||||
(output 's2' 10.0:8)
|
||||
(output 's1' 10.0:8)
|
||||
(output 's2' 11.0:8)
|
||||
(output 's3' 12.0:8)
|
||||
(output 's4' 11.0:8)
|
||||
(output 's4' 13.0:8)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(input 's5' 2:10)
|
||||
(input 's6' 10:18)
|
||||
(input 's7' 18:26)
|
||||
(output 's1' 9.0:8)
|
||||
(output 's2' 10.0:8)
|
||||
(output 's1' 10.0:8)
|
||||
(output 's2' 11.0:8)
|
||||
(output 's3' 12.0:8)
|
||||
(output 's4' 11.0:8)
|
||||
(output 's4' 13.0:8)
|
||||
))
|
||||
(cell 1 0 (matches 0.2:6 0001))
|
||||
(cell 2 0 (matches 0.2:6 0010 0011))
|
||||
(cell 3 0 (matches 0.2:6 11--))
|
||||
(cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
|
||||
(cell 5 0 (matches 0.6:10 0100))
|
||||
(cell 6 0 (matches 0.6:10 0101))
|
||||
(cell 7 0 (matches 0.6:10 0110))
|
||||
(cell 8 0 (priority_match 1 (cat 5.0 6.0 7.0 1'd1)))
|
||||
(cell 9 0 (assignment_list 8'd0 (4.0 0:8 0.10:18) (8.0 0:8 0.18:26)))
|
||||
(cell 10 0 (assignment_list 8'd0 (4.1 0:8 0.10:18) (8.1 0:8 0.18:26)))
|
||||
(cell 11 0 (assignment_list 8'd0 (4.2 0:8 0.10:18) (8.3 0:8 0.18:26)))
|
||||
(cell 12 0 (assignment_list 8'd0 (8.2 0:8 0.18:26)))
|
||||
(cell 3 0 (matches 0.2:6 ))
|
||||
(cell 4 0 (matches 0.2:6 11--))
|
||||
(cell 5 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0)))
|
||||
(cell 6 0 (matches 0.6:10 0100))
|
||||
(cell 7 0 (matches 0.6:10 0101))
|
||||
(cell 8 0 (matches 0.6:10 0110))
|
||||
(cell 9 0 (priority_match 1 (cat 6.0 7.0 8.0 1'd1)))
|
||||
(cell 10 0 (assignment_list 8'd0 (5.0 0:8 0.10:18) (9.0 0:8 0.18:26)))
|
||||
(cell 11 0 (assignment_list 8'd0 (5.1 0:8 0.10:18) (9.1 0:8 0.18:26)))
|
||||
(cell 12 0 (assignment_list 8'd0 (5.2 0:8 0.10:18) (9.2 0:8 0.18:26)))
|
||||
(cell 13 0 (assignment_list 8'd0 (5.3 0:8 0.10:18) (9.3 0:8 0.18:26)))
|
||||
)
|
||||
""")
|
||||
|
||||
|
|
@ -3042,7 +3043,7 @@ class RhsTestCase(FHDLTestCase):
|
|||
(input 'i8ud' 0.26:34)
|
||||
(input 'i4' 0.34:38)
|
||||
(output 'o1' (cat 5.0:8 2'd0))
|
||||
(output 'o2' (cat 9.0:8 2'd0))
|
||||
(output 'o2' (cat 10.0:8 2'd0))
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(input 'i8ua' 2:10)
|
||||
|
|
@ -3051,7 +3052,7 @@ class RhsTestCase(FHDLTestCase):
|
|||
(input 'i8ud' 26:34)
|
||||
(input 'i4' 34:38)
|
||||
(output 'o1' (cat 5.0:8 2'd0))
|
||||
(output 'o2' (cat 9.0:8 2'd0))
|
||||
(output 'o2' (cat 10.0:8 2'd0))
|
||||
))
|
||||
(cell 1 0 (matches 0.34:38 0001))
|
||||
(cell 2 0 (matches 0.34:38 0010 0011))
|
||||
|
|
@ -3063,12 +3064,14 @@ class RhsTestCase(FHDLTestCase):
|
|||
(4.2 0:8 0.18:26)
|
||||
))
|
||||
(cell 6 0 (matches 0.34:38 0100 0101))
|
||||
(cell 7 0 (matches 0.34:38 0110 0111))
|
||||
(cell 8 0 (priority_match 1 (cat 6.0 7.0 1'd1)))
|
||||
(cell 9 0 (assignment_list 8'd0
|
||||
(8.0 0:8 0.2:10)
|
||||
(8.1 0:8 0.18:26)
|
||||
(8.2 0:8 0.26:34)
|
||||
(cell 7 0 (matches 0.34:38 ))
|
||||
(cell 8 0 (matches 0.34:38 0110 0111))
|
||||
(cell 9 0 (priority_match 1 (cat 6.0 7.0 8.0 1'd1)))
|
||||
(cell 10 0 (assignment_list 8'd0
|
||||
(9.0 0:8 0.2:10)
|
||||
(9.1 0:8 0.10:18)
|
||||
(9.2 0:8 0.18:26)
|
||||
(9.3 0:8 0.26:34)
|
||||
))
|
||||
)
|
||||
""")
|
||||
|
|
|
|||
Loading…
Reference in a new issue