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back.rtlil: refactor to use intermediate structures.

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Fixes #1100.
This commit is contained in:
Wanda 2024-03-27 02:36:06 +01:00 • committed by Catherine
parent 81c35a5922
commit 2d59242bf7
4 changed files with 2244 additions and 325 deletions
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1834
tests/test_back_rtlil.py Normal file
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51
tests/test_hdl_ir.py
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@ -1632,32 +1632,33 @@ class AssignTestCase(FHDLTestCase):
(input 's5' 0.2:10)
(input 's6' 0.10:18)
(input 's7' 0.18:26)
(output 's1' 9.0:8)
(output 's2' 10.0:8)
(output 's1' 10.0:8)
(output 's2' 11.0:8)
(output 's3' 12.0:8)
(output 's4' 11.0:8)
(output 's4' 13.0:8)
)
(cell 0 0 (top
(input 's5' 2:10)
(input 's6' 10:18)
(input 's7' 18:26)
(output 's1' 9.0:8)
(output 's2' 10.0:8)
(output 's1' 10.0:8)
(output 's2' 11.0:8)
(output 's3' 12.0:8)
(output 's4' 11.0:8)
(output 's4' 13.0:8)
))
(cell 1 0 (matches 0.2:6 0001))
(cell 2 0 (matches 0.2:6 0010 0011))
(cell 3 0 (matches 0.2:6 11--))
(cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
(cell 5 0 (matches 0.6:10 0100))
(cell 6 0 (matches 0.6:10 0101))
(cell 7 0 (matches 0.6:10 0110))
(cell 8 0 (priority_match 1 (cat 5.0 6.0 7.0 1'd1)))
(cell 9 0 (assignment_list 8'd0 (4.0 0:8 0.10:18) (8.0 0:8 0.18:26)))
(cell 10 0 (assignment_list 8'd0 (4.1 0:8 0.10:18) (8.1 0:8 0.18:26)))
(cell 11 0 (assignment_list 8'd0 (4.2 0:8 0.10:18) (8.3 0:8 0.18:26)))
(cell 12 0 (assignment_list 8'd0 (8.2 0:8 0.18:26)))
(cell 3 0 (matches 0.2:6 ))
(cell 4 0 (matches 0.2:6 11--))
(cell 5 0 (priority_match 1 (cat 1.0 2.0 3.0 4.0)))
(cell 6 0 (matches 0.6:10 0100))
(cell 7 0 (matches 0.6:10 0101))
(cell 8 0 (matches 0.6:10 0110))
(cell 9 0 (priority_match 1 (cat 6.0 7.0 8.0 1'd1)))
(cell 10 0 (assignment_list 8'd0 (5.0 0:8 0.10:18) (9.0 0:8 0.18:26)))
(cell 11 0 (assignment_list 8'd0 (5.1 0:8 0.10:18) (9.1 0:8 0.18:26)))
(cell 12 0 (assignment_list 8'd0 (5.2 0:8 0.10:18) (9.2 0:8 0.18:26)))
(cell 13 0 (assignment_list 8'd0 (5.3 0:8 0.10:18) (9.3 0:8 0.18:26)))
)
""")
@ -3042,7 +3043,7 @@ class RhsTestCase(FHDLTestCase):
(input 'i8ud' 0.26:34)
(input 'i4' 0.34:38)
(output 'o1' (cat 5.0:8 2'd0))
(output 'o2' (cat 9.0:8 2'd0))
(output 'o2' (cat 10.0:8 2'd0))
)
(cell 0 0 (top
(input 'i8ua' 2:10)
@ -3051,7 +3052,7 @@ class RhsTestCase(FHDLTestCase):
(input 'i8ud' 26:34)
(input 'i4' 34:38)
(output 'o1' (cat 5.0:8 2'd0))
(output 'o2' (cat 9.0:8 2'd0))
(output 'o2' (cat 10.0:8 2'd0))
))
(cell 1 0 (matches 0.34:38 0001))
(cell 2 0 (matches 0.34:38 0010 0011))
@ -3063,12 +3064,14 @@ class RhsTestCase(FHDLTestCase):
(4.2 0:8 0.18:26)
))
(cell 6 0 (matches 0.34:38 0100 0101))
(cell 7 0 (matches 0.34:38 0110 0111))
(cell 8 0 (priority_match 1 (cat 6.0 7.0 1'd1)))
(cell 9 0 (assignment_list 8'd0
(8.0 0:8 0.2:10)
(8.1 0:8 0.18:26)
(8.2 0:8 0.26:34)
(cell 7 0 (matches 0.34:38 ))
(cell 8 0 (matches 0.34:38 0110 0111))
(cell 9 0 (priority_match 1 (cat 6.0 7.0 8.0 1'd1)))
(cell 10 0 (assignment_list 8'd0
(9.0 0:8 0.2:10)
(9.1 0:8 0.10:18)
(9.2 0:8 0.18:26)
(9.3 0:8 0.26:34)
))
)
""")