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hdl.cd: add negedge clock domains.

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Fixes #185.
This commit is contained in:
whitequark 2019-08-31 22:05:48 +00:00
parent c4e8ac734f
commit 2e20622046
4 changed files with 29 additions and 5 deletions
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5
nmigen/back/pysim.py
View file

@ -364,6 +364,7 @@ class Simulator:
self._slot_signals = list() # int/slot -> Signal
self._domains = list() # [ClockDomain]
self._clk_edges = dict() # ClockDomain -> int/edge
self._domain_triggers = list() # int/slot -> ClockDomain
self._signals = SignalSet() # {Signal}
@ -488,6 +489,7 @@ class Simulator:
add_fragment(subfragment, (*scope, name))
add_fragment(root_fragment, scope=("top",))
self._domains = list(domains)
self._clk_edges = {domain: 1 if domain.clk_edge == "pos" else 0 for domain in domains}
def add_signal(signal):
if signal not in self._signals:
@ -642,7 +644,8 @@ class Simulator:
return
# If the signal is a clock that triggers synchronous logic, record that fact.
if new == 1 and self._domain_triggers[signal_slot] is not None:
if (self._domain_triggers[signal_slot] is not None and
self._clk_edges[self._domain_triggers[signal_slot]] == new):
domains.add(self._domain_triggers[signal_slot])
if self._vcd_writer:

6
nmigen/back/rtlil.py
View file

@ -884,8 +884,8 @@ def _convert_fragment(builder, fragment, hierarchy):
# For every signal in every sync domain, assign \sig to \sig$next. The sensitivity
# list, however, differs between domains: for domains with sync reset, it is
# `posedge clk`, for sync domains with async reset it is `posedge clk or
# posedge rst`.
# `[pos|neg]edge clk`, for sync domains with async reset it is `[pos|neg]edge clk
# or posedge rst`.
for domain, signals in fragment.drivers.items():
if domain is None:
continue
@ -897,7 +897,7 @@ def _convert_fragment(builder, fragment, hierarchy):
cd = fragment.domains[domain]
triggers = []
triggers.append(("posedge", compiler_state.resolve_curr(cd.clk)))
triggers.append((cd.clk_edge + "edge", compiler_state.resolve_curr(cd.clk)))
if cd.async_reset:
triggers.append(("posedge", compiler_state.resolve_curr(cd.rst)))