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hdl.cd: add negedge clock domains.

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Fixes #185.
This commit is contained in:
whitequark 2019-08-31 22:05:48 +00:00
parent c4e8ac734f
commit 2e20622046
4 changed files with 29 additions and 5 deletions
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10
nmigen/hdl/cd.py
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@ -45,7 +45,8 @@ class ClockDomain:
else:
return "{}_{}".format(domain_name, signal_name)
def __init__(self, name=None, reset_less=False, async_reset=False, local=False):
def __init__(self, name=None, *, clk_edge="pos", reset_less=False, async_reset=False,
local=False):
if name is None:
try:
name = tracer.get_var_name()
@ -55,9 +56,16 @@ class ClockDomain:
name = name[3:]
if name == "comb":
raise ValueError("Domain '{}' may not be clocked".format(name))
if clk_edge not in ("pos", "neg"):
raise ValueError("Domain clock edge must be one of 'pos' or 'neg', not {!r}"
.format(clk_edge))
self.name = name
self.clk = Signal(name=self._name_for(name, "clk"), src_loc_at=1)
self.clk_edge = clk_edge
if reset_less:
self.rst = None
else: