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hdl.cd: add negedge clock domains.

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Fixes #185.
This commit is contained in:
whitequark 2019-08-31 22:05:48 +00:00
parent c4e8ac734f
commit 2e20622046
4 changed files with 29 additions and 5 deletions
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13
nmigen/test/test_hdl_cd.py
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@ -23,6 +23,19 @@ class ClockDomainTestCase(FHDLTestCase):
cd_reset = ClockDomain(local=True)
self.assertEqual(cd_reset.local, True)
def test_edge(self):
sync = ClockDomain()
self.assertEqual(sync.clk_edge, "pos")
sync = ClockDomain(clk_edge="pos")
self.assertEqual(sync.clk_edge, "pos")
sync = ClockDomain(clk_edge="neg")
self.assertEqual(sync.clk_edge, "neg")
def test_edge_wrong(self):
with self.assertRaises(ValueError,
msg="Domain clock edge must be one of 'pos' or 'neg', not 'xxx'"):
ClockDomain("sync", clk_edge="xxx")
def test_with_reset(self):
pix = ClockDomain()
self.assertIsNotNone(pix.clk)