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hdl.dsl: fix src_loc_at for FSM state signal.

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whitequark 2019-07-03 16:34:31 +00:00
parent 82903e493a
commit 2e4cc47fcb
1 changed files with 1 additions and 1 deletions
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2
nmigen/hdl/dsl.py
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@ -248,7 +248,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
self._check_context("FSM", context=None) self._check_context("FSM", context=None)
fsm_data = self._set_ctrl("FSM", { fsm_data = self._set_ctrl("FSM", {
"name": name, "name": name,
"signal": Signal(name="{}_state".format(name)), "signal": Signal(name="{}_state".format(name), src_loc_at=2),
"reset": reset, "reset": reset,
"domain": domain, "domain": domain,
"encoding": OrderedDict(), "encoding": OrderedDict(),