hdl._ast: change Switch to operate on list of cases.
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cd6cbd71ca
commit
2eb62a8b49
8 changed files with 95 additions and 90 deletions
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@ -1687,38 +1687,38 @@ class AssertTestCase(FHDLTestCase):
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class SwitchTestCase(FHDLTestCase):
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def test_default_case(self):
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s = Switch(Const(0), {None: []})
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self.assertEqual(s.cases, {(): []})
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s = Switch(Const(0), [(None, [], None)])
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self.assertEqual(s.cases, ((None, [], None),))
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def test_int_case(self):
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s = Switch(Const(0, 8), {10: []})
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self.assertEqual(s.cases, {("00001010",): []})
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s = Switch(Const(0, 8), [(10, [], None)])
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self.assertEqual(s.cases, ((("00001010",), [], None),))
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def test_int_neg_case(self):
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s = Switch(Const(0, signed(8)), {-10: []})
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self.assertEqual(s.cases, {("11110110",): []})
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s = Switch(Const(0, signed(8)), [(-10, [], None)])
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self.assertEqual(s.cases, ((("11110110",), [], None),))
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def test_int_zero_width(self):
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s = Switch(Const(0, 0), {0: []})
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self.assertEqual(s.cases, {("",): []})
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s = Switch(Const(0, 0), [(0, [], None)])
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self.assertEqual(s.cases, ((("",), [], None),))
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def test_int_zero_width_enum(self):
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class ZeroEnum(Enum):
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A = 0
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s = Switch(Const(0, 0), {ZeroEnum.A: []})
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self.assertEqual(s.cases, {("",): []})
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s = Switch(Const(0, 0), [(ZeroEnum.A, [], None)])
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self.assertEqual(s.cases, ((("",), [], None),))
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def test_enum_case(self):
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s = Switch(Const(0, UnsignedEnum), {UnsignedEnum.FOO: []})
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self.assertEqual(s.cases, {("01",): []})
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s = Switch(Const(0, UnsignedEnum), [(UnsignedEnum.FOO, [], None)])
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self.assertEqual(s.cases, ((("01",), [], None),))
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def test_str_case(self):
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s = Switch(Const(0, 8), {"0000 11\t01": []})
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self.assertEqual(s.cases, {("00001101",): []})
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s = Switch(Const(0, 8), [("0000 11\t01", [], None)])
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self.assertEqual(s.cases, ((("00001101",), [], None),))
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def test_two_cases(self):
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s = Switch(Const(0, 8), {("00001111", 123): []})
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self.assertEqual(s.cases, {("00001111", "01111011"): []})
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s = Switch(Const(0, 8), [(("00001111", 123), [], None)])
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self.assertEqual(s.cases, ((("00001111", "01111011"), [], None),))
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class IOValueTestCase(FHDLTestCase):
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@ -411,6 +411,7 @@ class DSLTestCase(FHDLTestCase):
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(
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(switch (sig w1)
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(case 0011 (eq (sig c1) (const 1'd1)))
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(case () (eq (sig c2) (const 1'd1)))
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)
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)
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""")
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@ -500,7 +501,14 @@ class DSLTestCase(FHDLTestCase):
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r"match value shape \(unsigned\(4\)\); comparison will never be true$"):
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with m.Case(Color.RED):
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m.d.comb += dummy.eq(0)
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self.assertEqual(m._statements, {})
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self.assertRepr(m._statements["comb"], """
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(
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(switch (sig w1)
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(case () (eq (sig dummy) (const 1'd0)))
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(case () (eq (sig dummy) (const 1'd0)))
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)
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)
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""")
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def test_Switch_zero_width(self):
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m = Module()
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