hdl._ast: change Switch to operate on list of cases.

This commit is contained in:
Wanda 2024-04-02 23:04:56 +02:00 committed by Catherine
parent cd6cbd71ca
commit 2eb62a8b49
8 changed files with 95 additions and 90 deletions

View file

@ -1687,38 +1687,38 @@ class AssertTestCase(FHDLTestCase):
class SwitchTestCase(FHDLTestCase):
def test_default_case(self):
s = Switch(Const(0), {None: []})
self.assertEqual(s.cases, {(): []})
s = Switch(Const(0), [(None, [], None)])
self.assertEqual(s.cases, ((None, [], None),))
def test_int_case(self):
s = Switch(Const(0, 8), {10: []})
self.assertEqual(s.cases, {("00001010",): []})
s = Switch(Const(0, 8), [(10, [], None)])
self.assertEqual(s.cases, ((("00001010",), [], None),))
def test_int_neg_case(self):
s = Switch(Const(0, signed(8)), {-10: []})
self.assertEqual(s.cases, {("11110110",): []})
s = Switch(Const(0, signed(8)), [(-10, [], None)])
self.assertEqual(s.cases, ((("11110110",), [], None),))
def test_int_zero_width(self):
s = Switch(Const(0, 0), {0: []})
self.assertEqual(s.cases, {("",): []})
s = Switch(Const(0, 0), [(0, [], None)])
self.assertEqual(s.cases, ((("",), [], None),))
def test_int_zero_width_enum(self):
class ZeroEnum(Enum):
A = 0
s = Switch(Const(0, 0), {ZeroEnum.A: []})
self.assertEqual(s.cases, {("",): []})
s = Switch(Const(0, 0), [(ZeroEnum.A, [], None)])
self.assertEqual(s.cases, ((("",), [], None),))
def test_enum_case(self):
s = Switch(Const(0, UnsignedEnum), {UnsignedEnum.FOO: []})
self.assertEqual(s.cases, {("01",): []})
s = Switch(Const(0, UnsignedEnum), [(UnsignedEnum.FOO, [], None)])
self.assertEqual(s.cases, ((("01",), [], None),))
def test_str_case(self):
s = Switch(Const(0, 8), {"0000 11\t01": []})
self.assertEqual(s.cases, {("00001101",): []})
s = Switch(Const(0, 8), [("0000 11\t01", [], None)])
self.assertEqual(s.cases, ((("00001101",), [], None),))
def test_two_cases(self):
s = Switch(Const(0, 8), {("00001111", 123): []})
self.assertEqual(s.cases, {("00001111", "01111011"): []})
s = Switch(Const(0, 8), [(("00001111", 123), [], None)])
self.assertEqual(s.cases, ((("00001111", "01111011"), [], None),))
class IOValueTestCase(FHDLTestCase):

View file

@ -411,6 +411,7 @@ class DSLTestCase(FHDLTestCase):
(
(switch (sig w1)
(case 0011 (eq (sig c1) (const 1'd1)))
(case () (eq (sig c2) (const 1'd1)))
)
)
""")
@ -500,7 +501,14 @@ class DSLTestCase(FHDLTestCase):
r"match value shape \(unsigned\(4\)\); comparison will never be true$"):
with m.Case(Color.RED):
m.d.comb += dummy.eq(0)
self.assertEqual(m._statements, {})
self.assertRepr(m._statements["comb"], """
(
(switch (sig w1)
(case () (eq (sig dummy) (const 1'd0)))
(case () (eq (sig dummy) (const 1'd0)))
)
)
""")
def test_Switch_zero_width(self):
m = Module()