hdl._ast: change Switch to operate on list of cases.
This commit is contained in:
Wanda
Catherine
parent
cd6cbd71ca
commit
2eb62a8b49
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@ -638,6 +638,8 @@ class ModuleEmitter:
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assert isinstance(matches_cell, _nir.Matches)
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assert test == matches_cell.value
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patterns = matches_cell.patterns
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# RTLIL cannot support empty pattern sets.
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assert patterns
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with switch.case(*patterns) as subcase:
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emit_assignments(subcase, subcond)
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emitted_switch = True
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@ -2763,38 +2763,34 @@ class _LateBoundStatement(Statement):
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@final
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class Switch(Statement):
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def __init__(self, test, cases, *, src_loc=None, src_loc_at=0, case_src_locs={}):
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def __init__(self, test, cases, *, src_loc=None, src_loc_at=0):
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if src_loc is None:
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super().__init__(src_loc_at=src_loc_at)
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else:
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# Switch is a bit special in terms of location tracking because it is usually created
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# long after the control has left the statement that directly caused its creation.
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self.src_loc = src_loc
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# Switch is also a bit special in that its parts also have location information. It can't
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# be automatically traced, so whatever constructs a Switch may optionally provide it.
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self.case_src_locs = {}
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self._test = Value.cast(test)
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self._cases = OrderedDict()
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for orig_keys, stmts in cases.items():
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# Map: None -> (); key -> (key,); (key...) -> (key...)
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keys = orig_keys
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if keys is None:
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keys = ()
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if not isinstance(keys, tuple):
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keys = (keys,)
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# Map: 2 -> "0010"; "0010" -> "0010"
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new_keys = ()
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key_mask = (1 << len(self.test)) - 1
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for key in _normalize_patterns(keys, self._test.shape()):
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if isinstance(key, int):
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key = to_binary(key & key_mask, len(self.test))
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new_keys = (*new_keys, key)
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self._cases = []
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for patterns, stmts, case_src_loc in cases:
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if patterns is not None:
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# Map: key -> (key,); (key...) -> (key...)
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if not isinstance(patterns, tuple):
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patterns = (patterns,)
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# Map: 2 -> "0010"; "0010" -> "0010"
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new_patterns = ()
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key_mask = (1 << len(self.test)) - 1
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for key in _normalize_patterns(patterns, self._test.shape()):
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if isinstance(key, int):
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key = to_binary(key & key_mask, len(self.test))
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new_patterns = (*new_patterns, key)
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else:
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new_patterns = None
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if not isinstance(stmts, Iterable):
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stmts = [stmts]
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self._cases[new_keys] = Statement.cast(stmts)
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if orig_keys in case_src_locs:
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self.case_src_locs[new_keys] = case_src_locs[orig_keys]
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self._cases.append((new_patterns, Statement.cast(stmts), case_src_loc))
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self._cases = tuple(self._cases)
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@property
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def test(self):
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@ -2805,22 +2801,22 @@ class Switch(Statement):
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return self._cases
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def _lhs_signals(self):
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return union((s._lhs_signals() for s in self.cases.values()), start=SignalSet())
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return union((stmts._lhs_signals() for _patterns, stmts, _src_loc in self.cases), start=SignalSet())
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def _rhs_signals(self):
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signals = union((s._rhs_signals() for s in self.cases.values()), start=SignalSet())
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signals = union((stmts._rhs_signals() for _patterns, stmts, _src_loc in self.cases), start=SignalSet())
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return self.test._rhs_signals() | signals
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def __repr__(self):
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def case_repr(keys, stmts):
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def case_repr(patterns, stmts):
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stmts_repr = " ".join(map(repr, stmts))
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if keys == ():
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if patterns is None:
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return f"(default {stmts_repr})"
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elif len(keys) == 1:
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return f"(case {keys[0]} {stmts_repr})"
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elif len(patterns) == 1:
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return f"(case {patterns[0]} {stmts_repr})"
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else:
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return "(case ({}) {})".format(" ".join(keys), stmts_repr)
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case_reprs = [case_repr(keys, stmts) for keys, stmts in self.cases.items()]
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return "(case ({}) {})".format(" ".join(patterns), stmts_repr)
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case_reprs = [case_repr(patterns, stmts) for patterns, stmts, _src_loc in self.cases]
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return "(switch {!r} {})".format(self.test, " ".join(case_reprs))
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@ -169,12 +169,11 @@ def resolve_statement(stmt):
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elif isinstance(stmt, Switch):
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return Switch(
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test=stmt.test,
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cases=OrderedDict(
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(patterns, resolve_statements(stmts))
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for patterns, stmts in stmt.cases.items()
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),
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cases=[
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(patterns, resolve_statements(stmts), src_loc)
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for patterns, stmts, src_loc in stmt.cases
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],
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src_loc=stmt.src_loc,
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case_src_locs=stmt.case_src_locs,
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)
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elif isinstance(stmt, (Assign, Property, Print)):
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return stmt
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@ -318,9 +317,9 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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self._check_context("Switch", context=None)
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switch_data = self._set_ctrl("Switch", {
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"test": Value.cast(test),
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"cases": OrderedDict(),
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"cases": [],
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"src_loc": tracer.get_src_loc(src_loc_at=1),
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"case_src_locs": {},
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"got_default": False,
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})
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try:
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self._ctrl_context = "Switch"
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@ -336,7 +335,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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self._check_context("Case", context="Switch")
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src_loc = tracer.get_src_loc(src_loc_at=1)
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switch_data = self._get_ctrl("Switch")
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if () in switch_data["cases"]:
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if switch_data["got_default"]:
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warnings.warn("A case defined after the default case will never be active",
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SyntaxWarning, stacklevel=3)
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new_patterns = _normalize_patterns(patterns, switch_data["test"].shape())
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@ -345,12 +344,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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self._ctrl_context = None
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yield
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self._flush_ctrl()
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# If none of the provided cases can possibly be true, omit this branch completely.
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# Likewise, omit this branch if another branch with this exact set of patterns already
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# exists (since otherwise we'd overwrite the previous branch's slot in the dict).
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if new_patterns and new_patterns not in switch_data["cases"]:
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switch_data["cases"][new_patterns] = self._statements
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switch_data["case_src_locs"][new_patterns] = src_loc
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switch_data["cases"].append((new_patterns, self._statements, src_loc))
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finally:
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self._ctrl_context = "Switch"
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self._statements = _outer_case
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@ -360,7 +354,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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self._check_context("Default", context="Switch")
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src_loc = tracer.get_src_loc(src_loc_at=1)
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switch_data = self._get_ctrl("Switch")
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if () in switch_data["cases"]:
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if switch_data["got_default"]:
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warnings.warn("A case defined after the default case will never be active",
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SyntaxWarning, stacklevel=3)
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try:
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@ -368,9 +362,8 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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self._ctrl_context = None
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yield
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self._flush_ctrl()
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if () not in switch_data["cases"]:
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switch_data["cases"][()] = self._statements
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switch_data["case_src_locs"][()] = src_loc
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switch_data["cases"].append((None, self._statements, src_loc))
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switch_data["got_default"] = True
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finally:
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self._ctrl_context = "Switch"
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self._statements = _outer_case
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@ -471,8 +464,8 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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domains[domain] = None
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for domain in domains:
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tests, cases = [], OrderedDict()
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for if_test, if_case in zip(if_tests + [None], if_bodies):
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tests, cases = [], []
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for if_test, if_case, if_src_loc in zip(if_tests + [None], if_bodies, if_src_locs):
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if if_test is not None:
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if len(if_test) != 1:
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if_test = if_test.bool()
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@ -482,27 +475,26 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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match = ("1" + "-" * (len(tests) - 1)).rjust(len(if_tests), "-")
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else:
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match = None
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cases[match] = if_case.get(domain, [])
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cases.append((match, if_case.get(domain, []), if_src_loc))
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self._statements.setdefault(domain, []).append(Switch(Cat(tests), cases,
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src_loc=src_loc, case_src_locs=dict(zip(cases, if_src_locs))))
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src_loc=src_loc))
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if name == "Switch":
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switch_test, switch_cases = data["test"], data["cases"]
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switch_case_src_locs = data["case_src_locs"]
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domains = {}
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for stmts in switch_cases.values():
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for _patterns, stmts, _src_loc in switch_cases:
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for domain in stmts:
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domains[domain] = None
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for domain in domains:
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domain_cases = OrderedDict()
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for patterns, stmts in switch_cases.items():
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domain_cases[patterns] = stmts.get(domain, [])
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domain_cases = []
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for patterns, stmts, case_src_loc in switch_cases:
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domain_cases.append((patterns, stmts.get(domain, []), case_src_loc))
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self._statements.setdefault(domain, []).append(Switch(switch_test, domain_cases,
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src_loc=src_loc, case_src_locs=switch_case_src_locs))
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src_loc=src_loc))
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if name == "FSM":
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fsm_name, fsm_init, fsm_encoding, fsm_decoding, fsm_states, fsm_ongoing = \
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@ -536,9 +528,11 @@ class Module(_ModuleBuilderRoot, Elaboratable):
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domain_states[state] = stmts.get(domain, [])
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self._statements.setdefault(domain, []).append(Switch(fsm_signal,
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OrderedDict((fsm_encoding[name], stmts) for name, stmts in domain_states.items()),
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src_loc=src_loc, case_src_locs={fsm_encoding[name]: fsm_state_src_locs[name]
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for name in fsm_states}))
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[
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(fsm_encoding[name], stmts, fsm_state_src_locs[name])
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for name, stmts in domain_states.items()
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],
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src_loc=src_loc))
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def _add_statement(self, assigns, domain, depth):
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while len(self._ctrl_stack) > self.domain._depth:
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@ -1110,20 +1110,25 @@ class NetlistEmitter:
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elif isinstance(stmt, _ast.Switch):
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test, _signed = self.emit_rhs(module_idx, stmt.test)
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conds = []
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for patterns in stmt.cases:
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if patterns:
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case_stmts = []
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for patterns, stmts, case_src_loc in stmt.cases:
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if patterns is not None:
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if not patterns:
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# Hack: empty pattern set cannot be supported by RTLIL.
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continue
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for pattern in patterns:
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assert len(pattern) == len(test)
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cell = _nir.Matches(module_idx, value=test, patterns=patterns,
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src_loc=stmt.case_src_locs.get(patterns))
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src_loc=case_src_loc)
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net, = self.netlist.add_value_cell(1, cell)
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conds.append(net)
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else:
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conds.append(_nir.Net.from_const(1))
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case_stmts.append(stmts)
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cell = _nir.PriorityMatch(module_idx, en=cond, inputs=_nir.Value(conds),
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src_loc=stmt.src_loc)
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conds = self.netlist.add_value_cell(len(conds), cell)
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for subcond, substmts in zip(conds, stmt.cases.values()):
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for subcond, substmts in zip(conds, case_stmts):
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for substmt in substmts:
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self.emit_stmt(module_idx, fragment, domain, substmt, subcond)
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else:
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@ -183,8 +183,6 @@ class StatementVisitor(metaclass=ABCMeta):
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new_stmt = self.on_unknown_statement(stmt)
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if isinstance(new_stmt, Statement) and self.replace_statement_src_loc(stmt, new_stmt):
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new_stmt.src_loc = stmt.src_loc
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if isinstance(new_stmt, Switch) and isinstance(stmt, Switch):
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new_stmt.case_src_locs = stmt.case_src_locs
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if isinstance(new_stmt, (Print, Property)):
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new_stmt._MustUse__used = True
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return new_stmt
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@ -221,7 +219,7 @@ class StatementTransformer(StatementVisitor):
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return Property(stmt.kind, self.on_value(stmt.test), message)
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def on_Switch(self, stmt):
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cases = OrderedDict((k, self.on_statement(s)) for k, s in stmt.cases.items())
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cases = [(k, self.on_statement(s), l) for k, s, l in stmt.cases]
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return Switch(self.on_value(stmt.test), cases)
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def on_statements(self, stmts):
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@ -429,7 +427,7 @@ class DomainCollector(ValueVisitor, StatementVisitor):
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def on_Switch(self, stmt):
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self.on_value(stmt.test)
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for stmts in stmt.cases.values():
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for _patterns, stmts, _src_loc in stmt.cases:
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self.on_statement(stmts)
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def on_statements(self, stmts):
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@ -624,7 +622,7 @@ class _ControlInserter(FragmentTransformer):
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class ResetInserter(_ControlInserter):
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def _insert_control(self, fragment, domain, signals):
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stmts = [s.eq(Const(s.init, s.shape())) for s in signals if not s.reset_less]
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fragment.add_statements(domain, Switch(self.controls[domain], {1: stmts}, src_loc=self.src_loc))
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fragment.add_statements(domain, Switch(self.controls[domain], [(1, stmts, None)], src_loc=self.src_loc))
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class EnableInserter(_ControlInserter):
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@ -632,7 +630,7 @@ class EnableInserter(_ControlInserter):
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if domain in fragment.statements:
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fragment.statements[domain] = _StatementList([Switch(
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self.controls[domain],
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{1: fragment.statements[domain]},
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[(1, fragment.statements[domain], None)],
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src_loc=self.src_loc,
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)])
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@ -396,10 +396,12 @@ class _StatementCompiler(StatementVisitor, _Compiler):
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def on_Switch(self, stmt):
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gen_test_value = self.rhs(stmt.test) # check for oversized value before generating mask
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gen_test = self.emitter.def_var("test", f"{(1 << len(stmt.test)) - 1:#x} & {gen_test_value}")
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for index, (patterns, stmts) in enumerate(stmt.cases.items()):
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for index, (patterns, stmts, _src_loc) in enumerate(stmt.cases):
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gen_checks = []
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if not patterns:
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if patterns is None:
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gen_checks.append(f"True")
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elif not patterns:
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gen_checks.append(f"False")
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else:
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for pattern in patterns:
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if "-" in pattern:
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@ -1687,38 +1687,38 @@ class AssertTestCase(FHDLTestCase):
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class SwitchTestCase(FHDLTestCase):
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def test_default_case(self):
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s = Switch(Const(0), {None: []})
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self.assertEqual(s.cases, {(): []})
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s = Switch(Const(0), [(None, [], None)])
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self.assertEqual(s.cases, ((None, [], None),))
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def test_int_case(self):
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s = Switch(Const(0, 8), {10: []})
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self.assertEqual(s.cases, {("00001010",): []})
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s = Switch(Const(0, 8), [(10, [], None)])
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self.assertEqual(s.cases, ((("00001010",), [], None),))
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def test_int_neg_case(self):
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s = Switch(Const(0, signed(8)), {-10: []})
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self.assertEqual(s.cases, {("11110110",): []})
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s = Switch(Const(0, signed(8)), [(-10, [], None)])
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self.assertEqual(s.cases, ((("11110110",), [], None),))
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def test_int_zero_width(self):
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s = Switch(Const(0, 0), {0: []})
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self.assertEqual(s.cases, {("",): []})
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s = Switch(Const(0, 0), [(0, [], None)])
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self.assertEqual(s.cases, ((("",), [], None),))
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def test_int_zero_width_enum(self):
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class ZeroEnum(Enum):
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A = 0
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s = Switch(Const(0, 0), {ZeroEnum.A: []})
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self.assertEqual(s.cases, {("",): []})
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s = Switch(Const(0, 0), [(ZeroEnum.A, [], None)])
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self.assertEqual(s.cases, ((("",), [], None),))
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def test_enum_case(self):
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s = Switch(Const(0, UnsignedEnum), {UnsignedEnum.FOO: []})
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self.assertEqual(s.cases, {("01",): []})
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s = Switch(Const(0, UnsignedEnum), [(UnsignedEnum.FOO, [], None)])
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self.assertEqual(s.cases, ((("01",), [], None),))
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def test_str_case(self):
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s = Switch(Const(0, 8), {"0000 11\t01": []})
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self.assertEqual(s.cases, {("00001101",): []})
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s = Switch(Const(0, 8), [("0000 11\t01", [], None)])
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self.assertEqual(s.cases, ((("00001101",), [], None),))
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def test_two_cases(self):
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s = Switch(Const(0, 8), {("00001111", 123): []})
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self.assertEqual(s.cases, {("00001111", "01111011"): []})
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s = Switch(Const(0, 8), [(("00001111", 123), [], None)])
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self.assertEqual(s.cases, ((("00001111", "01111011"), [], None),))
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class IOValueTestCase(FHDLTestCase):
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@ -411,6 +411,7 @@ class DSLTestCase(FHDLTestCase):
|
|||
(
|
||||
(switch (sig w1)
|
||||
(case 0011 (eq (sig c1) (const 1'd1)))
|
||||
(case () (eq (sig c2) (const 1'd1)))
|
||||
)
|
||||
)
|
||||
""")
|
||||
|
|
@ -500,7 +501,14 @@ class DSLTestCase(FHDLTestCase):
|
|||
r"match value shape \(unsigned\(4\)\); comparison will never be true$"):
|
||||
with m.Case(Color.RED):
|
||||
m.d.comb += dummy.eq(0)
|
||||
self.assertEqual(m._statements, {})
|
||||
self.assertRepr(m._statements["comb"], """
|
||||
(
|
||||
(switch (sig w1)
|
||||
(case () (eq (sig dummy) (const 1'd0)))
|
||||
(case () (eq (sig dummy) (const 1'd0)))
|
||||
)
|
||||
)
|
||||
""")
|
||||
|
||||
def test_Switch_zero_width(self):
|
||||
m = Module()
|
||||
|
|
|
|||
Loading…
Reference in a new issue