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back.pysim: synchronize waveform writing with cxxrtl.

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This commit is contained in:
whitequark 2020-07-07 04:06:06 +00:00
parent e012e62ade
commit 2efeb05c63
2 changed files with 13 additions and 29 deletions
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12
nmigen/test/test_sim.py
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@ -777,18 +777,6 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
with sim.write_vcd(open(os.path.devnull, "wt")):
pass
def test_vcd_wrong_twice(self):
s = Signal()
m = Module()
m.d.sync += s.eq(s)
sim = Simulator(m)
sim.add_clock(1e-6)
with self.assertRaisesRegex(ValueError,
r"^Already writing waveforms to .+$"):
with sim.write_vcd(open(os.path.devnull, "wt")):
with sim.write_vcd(open(os.path.devnull, "wt")):
pass
class SimulatorRegressionTestCase(FHDLTestCase):
def test_bug_325(self):