{,_}tools→{,_}utils

In context of nMigen, "tools" means "parts of toolchain", so it is
confusing to have a completely unrelated module also called "tools".

nmigen/_utils.py

@@ -5,7 +5,7 @@ from collections import OrderedDict
 from collections.abc import Iterable
 from contextlib import contextmanager
 
-from .tools import *
+from .utils import *
 
 
 __all__ = ["flatten", "union" , "log2_int", "bits_for", "memoize", "final", "deprecated"]

nmigen/back/pysim.py

@@ -6,7 +6,7 @@ from bitarray import bitarray
 from vcd import VCDWriter
 from vcd.gtkw import GTKWSave
 
-from .._tools import flatten
+from .._utils import flatten
 from ..hdl.ast import *
 from ..hdl.ir import *
 from ..hdl.xfrm import ValueVisitor, StatementVisitor

nmigen/back/rtlil.py

@@ -3,7 +3,7 @@ import textwrap
 from collections import defaultdict, OrderedDict
 from contextlib import contextmanager
 
-from .._tools import bits_for, flatten
+from .._utils import bits_for, flatten
 from ..hdl import ast, rec, ir, mem, xfrm
 
 

nmigen/compat/fhdl/bitcontainer.py

@@ -1,19 +1,19 @@
-from ... import tools
+from ... import utils
 from ...hdl import ast
-from ..._tools import deprecated
+from ..._utils import deprecated
 
 
 __all__ = ["log2_int", "bits_for", "value_bits_sign"]
 
 
-@deprecated("instead of `log2_int`, use `nmigen.tools.log2_int`")
+@deprecated("instead of `log2_int`, use `nmigen.utils.log2_int`")
 def log2_int(n, need_pow2=True):
-    return tools.log2_int(n, need_pow2)
+    return utils.log2_int(n, need_pow2)
 
 
-@deprecated("instead of `bits_for`, use `nmigen.tools.bits_for`")
+@deprecated("instead of `bits_for`, use `nmigen.utils.bits_for`")
 def bits_for(n, require_sign_bit=False):
-    return tools.bits_for(n, require_sign_bit)
+    return utils.bits_for(n, require_sign_bit)
 
 
 @deprecated("instead of `value_bits_sign(v)`, use `v.shape()`")

nmigen/compat/fhdl/decorators.py

@@ -2,7 +2,7 @@ from ...hdl.ast import *
 from ...hdl.xfrm import ResetInserter as NativeResetInserter
 from ...hdl.xfrm import EnableInserter as NativeEnableInserter
 from ...hdl.xfrm import DomainRenamer as NativeDomainRenamer
-from ..._tools import deprecated
+from ..._utils import deprecated
 
 
 __all__ = ["ResetInserter", "CEInserter", "ClockDomainsRenamer"]

nmigen/compat/fhdl/module.py

@@ -1,6 +1,6 @@
 from collections.abc import Iterable
 
-from ..._tools import flatten, deprecated
+from ..._utils import flatten, deprecated
 from ...hdl import dsl, ir
 
 

nmigen/compat/fhdl/specials.py

@@ -1,6 +1,6 @@
 import warnings
 
-from ..._tools import deprecated, extend
+from ..._utils import deprecated, extend
 from ...hdl.ast import *
 from ...hdl.ir import Elaboratable
 from ...hdl.mem import Memory as NativeMemory

nmigen/compat/fhdl/structure.py

@@ -1,6 +1,6 @@
 from collections import OrderedDict
 
-from ..._tools import deprecated, extend
+from ..._utils import deprecated, extend
 from ...hdl import ast
 from ...hdl.ast import (DUID, Value, Signal, Mux, Slice as _Slice, Cat, Repl, Const, C,
                         ClockSignal, ResetSignal,

nmigen/compat/genlib/cdc.py

@@ -1,6 +1,6 @@
 import warnings
 
-from ..._tools import deprecated
+from ..._utils import deprecated
 from ...lib.cdc import FFSynchronizer as NativeFFSynchronizer
 from ...hdl.ast import *
 from ..fhdl.module import CompatModule

nmigen/compat/genlib/fifo.py

@@ -1,4 +1,4 @@
-from ..._tools import deprecated, extend
+from ..._utils import deprecated, extend
 from ...lib.fifo import (FIFOInterface as NativeFIFOInterface,
   SyncFIFO as NativeSyncFIFO, SyncFIFOBuffered as NativeSyncFIFOBuffered,
   AsyncFIFO as NativeAsyncFIFO, AsyncFIFOBuffered as NativeAsyncFIFOBuffered)

nmigen/compat/genlib/fsm.py

@@ -1,6 +1,6 @@
 from collections import OrderedDict
 
-from ..._tools import deprecated, _ignore_deprecated
+from ..._utils import deprecated, _ignore_deprecated
 from ...hdl.xfrm import ValueTransformer, StatementTransformer
 from ...hdl.ast import *
 from ..fhdl.module import CompatModule, CompatFinalizeError

nmigen/compat/genlib/resetsync.py

@@ -1,4 +1,4 @@
-from ..._tools import deprecated
+from ..._utils import deprecated
 from ...lib.cdc import ResetSynchronizer as NativeResetSynchronizer
 
 

nmigen/hdl/ast.py

@@ -8,7 +8,7 @@ from collections.abc import Iterable, MutableMapping, MutableSet, MutableSequenc
 from enum import Enum
 
 from .. import tracer
-from .._tools import *
+from .._utils import *
 
 
 __all__ = [

nmigen/hdl/dsl.py

@@ -4,7 +4,7 @@ from contextlib import contextmanager
 from enum import Enum
 import warnings
 
-from .._tools import flatten, bits_for, deprecated
+from .._utils import flatten, bits_for, deprecated
 from .. import tracer
 from .ast import *
 from .ir import *

nmigen/hdl/ir.py

@@ -5,7 +5,7 @@ import warnings
 import traceback
 import sys
 
-from .._tools import *
+from .._utils import *
 from .ast import *
 from .cd import *
 

nmigen/hdl/rec.py

@@ -3,7 +3,7 @@ from collections import OrderedDict
 from functools import reduce
 
 from .. import tracer
-from .._tools import union, deprecated
+from .._utils import union, deprecated
 from .ast import *
 
 

nmigen/hdl/xfrm.py

@@ -2,7 +2,7 @@ from abc import ABCMeta, abstractmethod
 from collections import OrderedDict
 from collections.abc import Iterable
 
-from .._tools import flatten, deprecated
+from .._utils import flatten, deprecated
 from .. import tracer
 from .ast import *
 from .ast import _StatementList

nmigen/lib/cdc.py

@@ -1,4 +1,4 @@
-from .._tools import deprecated
+from .._utils import deprecated
 from .. import *
 
 

nmigen/lib/fifo.py

@@ -2,7 +2,7 @@
 
 from .. import *
 from ..asserts import *
-from .._tools import log2_int, deprecated
+from .._utils import log2_int, deprecated
 from .coding import GrayEncoder
 from .cdc import FFSynchronizer
 

nmigen/test/compat/support.py

@@ -1,4 +1,4 @@
-from ..._tools import _ignore_deprecated
+from ..._utils import _ignore_deprecated
 from ...compat import *
 from ...compat.fhdl import verilog
 

nmigen/test/compat/test_size.py

@@ -1,6 +1,6 @@
 import unittest
 
-from ..._tools import _ignore_deprecated
+from ..._utils import _ignore_deprecated
 from ...compat import *
 
 

nmigen/test/test_build_dsl.py

@@ -1,7 +1,7 @@
 from collections import OrderedDict
 
 from ..build.dsl import *
-from .tools import *
+from .utils import *
 
 
 class PinsTestCase(FHDLTestCase):

nmigen/test/test_build_res.py

@@ -3,7 +3,7 @@ from ..hdl.rec import *
 from ..lib.io import *
 from ..build.dsl import *
 from ..build.res import *
-from .tools import *
+from .utils import *
 
 
 class ResourceManagerTestCase(FHDLTestCase):

nmigen/test/test_compat.py

@@ -1,6 +1,6 @@
 from ..hdl.ir import Fragment
 from ..compat import *
-from .tools import *
+from .utils import *
 
 
 class CompatTestCase(FHDLTestCase):

nmigen/test/test_examples.py

@@ -2,7 +2,7 @@ import sys
 import subprocess
 from pathlib import Path
 
-from .tools import *
+from .utils import *
 
 
 def example_test(name):

nmigen/test/test_hdl_ast.py

@@ -2,7 +2,7 @@ import warnings
 from enum import Enum
 
 from ..hdl.ast import *
-from .tools import *
+from .utils import *
 
 
 class UnsignedEnum(Enum):

nmigen/test/test_hdl_cd.py

@@ -1,5 +1,5 @@
 from ..hdl.cd import *
-from .tools import *
+from .utils import *
 
 
 class ClockDomainTestCase(FHDLTestCase):

nmigen/test/test_hdl_dsl.py

@@ -4,7 +4,7 @@ from enum import Enum
 from ..hdl.ast import *
 from ..hdl.cd import *
 from ..hdl.dsl import *
-from .tools import *
+from .utils import *
 
 
 class DSLTestCase(FHDLTestCase):

nmigen/test/test_hdl_ir.py

@@ -4,7 +4,7 @@ from ..hdl.ast import *
 from ..hdl.cd import *
 from ..hdl.ir import *
 from ..hdl.mem import *
-from .tools import *
+from .utils import *
 
 
 class BadElaboratable(Elaboratable):

nmigen/test/test_hdl_mem.py

@@ -1,6 +1,6 @@
 from ..hdl.ast import *
 from ..hdl.mem import *
-from .tools import *
+from .utils import *
 
 
 class MemoryTestCase(FHDLTestCase):

nmigen/test/test_hdl_rec.py

@@ -2,7 +2,7 @@ from enum import Enum
 
 from ..hdl.ast import *
 from ..hdl.rec import *
-from .tools import *
+from .utils import *
 
 
 class UnsignedEnum(Enum):

nmigen/test/test_hdl_xfrm.py

@@ -3,7 +3,7 @@ from ..hdl.cd import *
 from ..hdl.ir import *
 from ..hdl.xfrm import *
 from ..hdl.mem import *
-from .tools import *
+from .utils import *
 
 
 class DomainRenamerTestCase(FHDLTestCase):

nmigen/test/test_lib_cdc.py

@@ -1,4 +1,4 @@
-from .tools import *
+from .utils import *
 from ..hdl import *
 from ..back.pysim import *
 from ..lib.cdc import *

nmigen/test/test_lib_coding.py

@@ -1,4 +1,4 @@
-from .tools import *
+from .utils import *
 from ..hdl import *
 from ..asserts import *
 from ..back.pysim import *

nmigen/test/test_lib_fifo.py

@@ -1,4 +1,4 @@
-from .tools import *
+from .utils import *
 from ..hdl import *
 from ..asserts import *
 from ..back.pysim import *

nmigen/test/test_lib_io.py

@@ -1,4 +1,4 @@
-from .tools import *
+from .utils import *
 from ..hdl import *
 from ..hdl.rec import *
 from ..back.pysim import *

nmigen/test/test_sim.py

@@ -1,7 +1,7 @@
 from contextlib import contextmanager
 
-from .tools import *
-from .._tools import flatten, union
+from .utils import *
+from .._utils import flatten, union
 from ..hdl.ast import *
 from ..hdl.cd import  *
 from ..hdl.mem import *