parent
c7984463c7
commit
3180a17fd9
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@ -796,11 +796,11 @@ class Slice(Value):
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raise TypeError("Slice stop must be an integer, not {!r}".format(stop))
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n = len(value)
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if start not in range(-(n+1), n+1):
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if start not in range(-n, n+1):
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raise IndexError("Cannot start slice {} bits into {}-bit value".format(start, n))
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if start < 0:
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start += n
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if stop not in range(-(n+1), n+1):
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if stop not in range(-n, n+1):
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raise IndexError("Cannot stop slice {} bits into {}-bit value".format(stop, n))
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if stop < 0:
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stop += n
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@ -714,6 +714,9 @@ class SliceTestCase(FHDLTestCase):
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with self.assertRaisesRegex(IndexError,
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r"^Slice start 4 must be less than slice stop 2$"):
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Slice(c, 4, 2)
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with self.assertRaisesRegex(IndexError,
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r"^Cannot start slice -9 bits into 8-bit value$"):
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Slice(c, -9, -5)
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def test_repr(self):
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s1 = Const(10)[2]
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