parent
c7984463c7
commit
3180a17fd9
2 changed files with 5 additions and 2 deletions
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@ -714,6 +714,9 @@ class SliceTestCase(FHDLTestCase):
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with self.assertRaisesRegex(IndexError,
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r"^Slice start 4 must be less than slice stop 2$"):
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Slice(c, 4, 2)
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with self.assertRaisesRegex(IndexError,
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r"^Cannot start slice -9 bits into 8-bit value$"):
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Slice(c, -9, -5)
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def test_repr(self):
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s1 = Const(10)[2]
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