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hdl.mem: fix src_loc_at in ReadPort, WritePort.

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whitequark 2019-12-15 11:46:14 +00:00
parent 67650214b7
commit 318274d5a0
1 changed files with 5 additions and 5 deletions
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10
nmigen/hdl/mem.py
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@ -74,9 +74,9 @@ class ReadPort(Elaboratable):
self.transparent = transparent self.transparent = transparent
self.addr = Signal(range(memory.depth), self.addr = Signal(range(memory.depth),
name="{}_r_addr".format(memory.name), src_loc_at=2 + src_loc_at) name="{}_r_addr".format(memory.name), src_loc_at=1 + src_loc_at)
self.data = Signal(memory.width, self.data = Signal(memory.width,
name="{}_r_data".format(memory.name), src_loc_at=2 + src_loc_at) name="{}_r_data".format(memory.name), src_loc_at=1 + src_loc_at)
if self.domain != "comb" and not transparent: if self.domain != "comb" and not transparent:
self.en = Signal(name="{}_r_en".format(memory.name), reset=1, self.en = Signal(name="{}_r_en".format(memory.name), reset=1,
src_loc_at=2 + src_loc_at) src_loc_at=2 + src_loc_at)
@ -151,11 +151,11 @@ class WritePort(Elaboratable):
self.granularity = granularity self.granularity = granularity
self.addr = Signal(range(memory.depth), self.addr = Signal(range(memory.depth),
name="{}_w_addr".format(memory.name), src_loc_at=2 + src_loc_at) name="{}_w_addr".format(memory.name), src_loc_at=1 + src_loc_at)
self.data = Signal(memory.width, self.data = Signal(memory.width,
name="{}_w_data".format(memory.name), src_loc_at=2 + src_loc_at) name="{}_w_data".format(memory.name), src_loc_at=1 + src_loc_at)
self.en = Signal(memory.width // granularity, self.en = Signal(memory.width // granularity,
name="{}_w_en".format(memory.name), src_loc_at=2 + src_loc_at) name="{}_w_en".format(memory.name), src_loc_at=1 + src_loc_at)
def elaborate(self, platform): def elaborate(self, platform):
f = Instance("$memwr", f = Instance("$memwr",