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hdl.mem: add synthesis attribute support.

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Fixes #291.
This commit is contained in:
whitequark 2020-02-06 14:48:48 +00:00
parent f7abe368a9
commit 31cd72c0b6
3 changed files with 13 additions and 2 deletions
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6
nmigen/test/test_hdl_mem.py
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@ -42,6 +42,12 @@ class MemoryTestCase(FHDLTestCase):
"'str' object cannot be interpreted as an integer"):
m = Memory(width=8, depth=4, init=[1, "0"])
def test_attrs(self):
m1 = Memory(width=8, depth=4)
self.assertEqual(m1.attrs, {})
m2 = Memory(width=8, depth=4, attrs={"ram_block": True})
self.assertEqual(m2.attrs, {"ram_block": True})
def test_read_port_transparent(self):
mem = Memory(width=8, depth=4)
rdport = mem.read_port()