vendor.fpga.lattice_ice40: implement.
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nmigen/vendor/__init__.py
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nmigen/vendor/__init__.py
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nmigen/vendor/fpga/__init__.py
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nmigen/vendor/fpga/__init__.py
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134
nmigen/vendor/fpga/lattice_ice40.py
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nmigen/vendor/fpga/lattice_ice40.py
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from abc import abstractproperty
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import os
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import subprocess
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import tempfile
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from ...build import *
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__all__ = ["LatticeICE40Platform", "IceStormProgrammerMixin", "IceBurnProgrammerMixin"]
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class LatticeICE40Platform(TemplatedPlatform):
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"""
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Required tools:
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* ``yosys``
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* ``nextpnr-ice40``
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* ``icepack``
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Available overrides:
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* ``verbose``: enables logging of informational messages to standard error.
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* ``read_opts``: adds options for ``read`` Yosys command.
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* ``synth_opts``: adds options for ``synth_ice40`` Yosys command.
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* ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
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* ``script_after_synth``: inserts commands after ``synth_ice40`` in Yosys script.
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* ``yosys_opts``: overrides default options (``-q``) for Yosys.
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* ``nextpnr_opts``: overrides default options (``-q --placer heap``).
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Build products:
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* ``{{name}}.rpt``: Yosys log.
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* ``{{name}}.json``: synthesized RTL.
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* ``{{name}}.tim``: nextpnr log.
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* ``{{name}}.asc``: ASCII bitstream.
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* ``{{name}}.bin``: binary bitstream.
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"""
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device = abstractproperty()
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package = abstractproperty()
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file_templates = {
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**TemplatedPlatform.build_script_templates,
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"{{name}}.il": r"""
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# {{autogenerated}}
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{{emit_design("rtlil")}}
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""",
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"{{name}}.ys": r"""
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# {{autogenerated}}
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{% for file in platform.extra_files %}
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{% if file.endswith(".v") -%}
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read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
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{% elif file.endswith(".sv") -%}
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read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
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{% endif %}
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{% endfor %}
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read_ilang {{name}}.il
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{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
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synth_ice40 {{get_override("synth_opts")|join(" ")}} -top {{name}}
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{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
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write_json {{name}}.json
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""",
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"{{name}}.pcf": r"""
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# {{autogenerated}}
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{% for port, pins, extra in platform.iter_port_constraints() %}
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{% if pins|count > 1 %}
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{% for bit in range -%}
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set_io {{port}}[{{bit}}] {{pins[bit]}}
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{% endfor %}
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{% else -%}
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set_io {{port}} {{pins[0]}}
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{% endif %}
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{% endfor %}
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""",
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"{{name}}_pre_pack.py": r"""
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# {{autogenerated}}
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{% for port, frequency in platform.iter_clock_constraints() -%}
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{# Clock in MHz #}
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ctx.addClock("{{port}}", {{frequency/1000000}})
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{% endfor%}
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""",
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}
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command_templates = [
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r"""
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{{get_tool("yosys")}}
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{{quiet("-q")}}
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{{get_override("yosys_opts")|join(" ")}}
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-l {{name}}.rpt
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{{name}}.ys
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""",
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r"""
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{{get_tool("nextpnr-ice40")}}
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{{quiet("-q")}}
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{{get_override("nextpnr_opts")|default(["--placer","heap"])|join(" ")}}
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-l {{name}}.tim
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--{{platform.device}}
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--package {{platform.package}}
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--json {{name}}.json
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--pcf {{name}}.pcf
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--pre-pack {{name}}_pre_pack.py
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--asc {{name}}.asc
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""",
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r"""
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{{get_tool("icepack")}}
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{{name}}.asc
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{{name}}.bin
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"""
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]
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class IceStormProgrammerMixin:
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def toolchain_program(self, products, name, *, mode=None):
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if mode is None and hasattr(self, "prog_mode"):
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mode = self.prog_mode
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if mode not in ("sram", "flash"):
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raise ValueError("iceprog mode must be one of \"sram\" or \"flash\", not {!r}; "
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"specify it using .build(..., program_opts={\"mode\": \"<mode>\"})"
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.format(mode))
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iceprog = os.environ.get("ICEPROG", "iceprog")
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bitstream = products.get("{}.bin".format(name))
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if mode == "sram":
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options = ["-S"]
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if mode == "flash":
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options = []
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with tempfile.NamedTemporaryFile(prefix="nmigen_iceprog_") as bitstream_file:
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bitstream_file.write(bitstream)
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subprocess.run([iceprog, *options, bitstream_file.name], check=True)
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class IceBurnProgrammerMixin:
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def toolchain_program(self, products, name):
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iceburn = os.environ.get("ICEBURN", "iCEburn")
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bitstream = products.get("{}.bin".format(name))
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with tempfile.NamedTemporaryFile(prefix="nmigen_iceburn_") as bitstream_file:
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bitstream_file.write(bitstream)
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subprocess.run([iceburn, "-evw", bitstream_file.name], check=True)
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