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hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.

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This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
This commit is contained in:
whitequark 2019-06-28 04:37:08 +00:00
parent 48d4ee4031
commit 32446831b4
6 changed files with 73 additions and 55 deletions
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6
nmigen/compat/fhdl/structure.py
View file

@ -106,12 +106,12 @@ class Case(ast.Switch):
or choice > key):
key = choice
elif isinstance(key, str) and key == "default":
key = None
key = ()
else:
key = "{:0{}b}".format(wrap(key).value, len(self.test))
key = ("{:0{}b}".format(wrap(key).value, len(self.test)),)
stmts = self.cases[key]
del self.cases[key]
self.cases[None] = stmts
self.cases[()] = stmts
return self