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hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.

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This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
This commit is contained in:
whitequark 2019-06-28 04:37:08 +00:00
parent 48d4ee4031
commit 32446831b4
6 changed files with 73 additions and 55 deletions
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2
nmigen/test/test_hdl_dsl.py
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@ -297,7 +297,7 @@ class DSLTestCase(FHDLTestCase):
(
(switch (sig w1)
(case 0011 (eq (sig c1) (const 1'd1)))
(case ---- (eq (sig c2) (const 1'd1)))
(default (eq (sig c2) (const 1'd1)))
)
)
""")