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vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.

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This commit is contained in:
whitequark 2019-06-03 03:01:56 +00:00
parent f417725b10
commit 3327deae92
1 changed files with 1 additions and 1 deletions
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2
nmigen/vendor/fpga/lattice_ice40.py vendored
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@ -51,7 +51,7 @@ class LatticeICE40Platform(TemplatedPlatform):
{% if file.endswith(".v") -%}
read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
{% elif file.endswith(".sv") -%}
read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
{% endif %}
{% endfor %}
read_ilang {{name}}.il