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hdl.dsl: gracefully handle FSM with no states.

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This commit is contained in:
whitequark 2019-07-07 00:59:34 +00:00
parent 146f3cb684
commit 3388b5b085
2 changed files with 10 additions and 0 deletions
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8
nmigen/test/test_hdl_dsl.py
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@ -449,6 +449,14 @@ class DSLTestCase(FHDLTestCase):
)
""")
def test_FSM_empty(self):
m = Module()
with m.FSM():
pass
self.assertRepr(m._statements, """
()
""")
def test_FSM_wrong_redefined(self):
m = Module()
with m.FSM():