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hdl.dsl: gracefully handle FSM with no states.

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This commit is contained in:
whitequark 2019-07-07 00:59:34 +00:00
parent 146f3cb684
commit 3388b5b085
2 changed files with 10 additions and 0 deletions
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2
nmigen/hdl/dsl.py
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@ -337,6 +337,8 @@ class Module(_ModuleBuilderRoot, Elaboratable):
if name == "FSM": if name == "FSM":
fsm_signal, fsm_reset, fsm_encoding, fsm_decoding, fsm_states = \ fsm_signal, fsm_reset, fsm_encoding, fsm_decoding, fsm_states = \
data["signal"], data["reset"], data["encoding"], data["decoding"], data["states"] data["signal"], data["reset"], data["encoding"], data["decoding"], data["states"]
if not fsm_states:
return
fsm_signal.nbits = bits_for(len(fsm_encoding) - 1) fsm_signal.nbits = bits_for(len(fsm_encoding) - 1)
if fsm_reset is None: if fsm_reset is None:
fsm_signal.reset = fsm_encoding[next(iter(fsm_states))] fsm_signal.reset = fsm_encoding[next(iter(fsm_states))]

8
nmigen/test/test_hdl_dsl.py
View file

@ -449,6 +449,14 @@ class DSLTestCase(FHDLTestCase):
) )
""") """)
def test_FSM_empty(self):
m = Module()
with m.FSM():
pass
self.assertRepr(m._statements, """
()
""")
def test_FSM_wrong_redefined(self): def test_FSM_wrong_redefined(self):
m = Module() m = Module()
with m.FSM(): with m.FSM():