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vendor: give names to IO buffer instances.

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Fixes #123.
This commit is contained in:
whitequark 2019-07-03 14:43:03 +00:00
parent 5800f00776
commit 33f21628bb
4 changed files with 26 additions and 26 deletions
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16
nmigen/vendor/lattice_ecp5.py vendored
View file

@ -261,7 +261,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("IB", m.submodules[pin.name] = Instance("IB",
i_I=port[bit], i_I=port[bit],
o_O=i[bit] o_O=i[bit]
) )
@ -273,7 +273,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("OB", m.submodules[pin.name] = Instance("OB",
i_I=o[bit], i_I=o[bit],
o_O=port[bit] o_O=port[bit]
) )
@ -285,7 +285,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("OBZ", m.submodules[pin.name] = Instance("OBZ",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=port[bit] o_O=port[bit]
@ -299,7 +299,7 @@ class LatticeECP5Platform(TemplatedPlatform):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None, i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None) o_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("BB", m.submodules[pin.name] = Instance("BB",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=i[bit], o_O=i[bit],
@ -313,7 +313,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("IB", m.submodules[pin.name] = Instance("IB",
i_I=p_port[bit], i_I=p_port[bit],
o_O=i[bit] o_O=i[bit]
) )
@ -325,7 +325,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("OB", m.submodules[pin.name] = Instance("OB",
i_I=o[bit], i_I=o[bit],
o_O=p_port[bit], o_O=p_port[bit],
) )
@ -337,7 +337,7 @@ class LatticeECP5Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("OBZ", m.submodules[pin.name] = Instance("OBZ",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=p_port[bit], o_O=p_port[bit],
@ -351,7 +351,7 @@ class LatticeECP5Platform(TemplatedPlatform):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None, i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None) o_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("BB", m.submodules[pin.name] = Instance("BB",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=i[bit], o_O=i[bit],

4
nmigen/vendor/lattice_ice40.py vendored
View file

@ -248,9 +248,9 @@ class LatticeICE40Platform(TemplatedPlatform):
io_args.append(("i", "OUTPUT_ENABLE", pin.oe)) io_args.append(("i", "OUTPUT_ENABLE", pin.oe))
if is_global_input: if is_global_input:
m.submodules += Instance("SB_GB_IO", *io_args) m.submodules[pin.name] = Instance("SB_GB_IO", *io_args)
else: else:
m.submodules += Instance("SB_IO", *io_args) m.submodules[pin.name] = Instance("SB_IO", *io_args)
def get_input(self, pin, port, attrs, invert): def get_input(self, pin, port, attrs, invert):
self._check_feature("single-ended input", pin, attrs, self._check_feature("single-ended input", pin, attrs,

16
nmigen/vendor/xilinx_7series.py vendored
View file

@ -239,7 +239,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("IBUF", m.submodules[pin.name] = Instance("IBUF",
i_I=port[bit], i_I=port[bit],
o_O=i[bit] o_O=i[bit]
) )
@ -251,7 +251,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("OBUF", m.submodules[pin.name] = Instance("OBUF",
i_I=o[bit], i_I=o[bit],
o_O=port[bit] o_O=port[bit]
) )
@ -263,7 +263,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("OBUFT", m.submodules[pin.name] = Instance("OBUFT",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=port[bit] o_O=port[bit]
@ -277,7 +277,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None, i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None) o_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("IOBUF", m.submodules[pin.name] = Instance("IOBUF",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=i[bit], o_O=i[bit],
@ -291,7 +291,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("IBUFDS", m.submodules[pin.name] = Instance("IBUFDS",
i_I=p_port[bit], i_IB=n_port[bit], i_I=p_port[bit], i_IB=n_port[bit],
o_O=i[bit] o_O=i[bit]
) )
@ -303,7 +303,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("OBUFDS", m.submodules[pin.name] = Instance("OBUFDS",
i_I=o[bit], i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit] o_O=p_port[bit], o_OB=n_port[bit]
) )
@ -315,7 +315,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("OBUFTDS", m.submodules[pin.name] = Instance("OBUFTDS",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit] o_O=p_port[bit], o_OB=n_port[bit]
@ -329,7 +329,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None, i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None) o_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("IOBUFDS", m.submodules[pin.name] = Instance("IOBUFDS",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=i[bit], o_O=i[bit],

16
nmigen/vendor/xilinx_spartan6.py vendored
View file

@ -248,7 +248,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("IBUF", m.submodules[pin.name] = Instance("IBUF",
i_I=port[bit], i_I=port[bit],
o_O=i[bit] o_O=i[bit]
) )
@ -260,7 +260,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("OBUF", m.submodules[pin.name] = Instance("OBUF",
i_I=o[bit], i_I=o[bit],
o_O=port[bit] o_O=port[bit]
) )
@ -272,7 +272,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("OBUFT", m.submodules[pin.name] = Instance("OBUFT",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=port[bit] o_O=port[bit]
@ -286,7 +286,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None, i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None) o_invert=True if invert else None)
for bit in range(len(port)): for bit in range(len(port)):
m.submodules += Instance("IOBUF", m.submodules[pin.name] = Instance("IOBUF",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=i[bit], o_O=i[bit],
@ -300,7 +300,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("IBUFDS", m.submodules[pin.name] = Instance("IBUFDS",
i_I=p_port[bit], i_IB=n_port[bit], i_I=p_port[bit], i_IB=n_port[bit],
o_O=i[bit] o_O=i[bit]
) )
@ -312,7 +312,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("OBUFDS", m.submodules[pin.name] = Instance("OBUFDS",
i_I=o[bit], i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit] o_O=p_port[bit], o_OB=n_port[bit]
) )
@ -324,7 +324,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("OBUFTDS", m.submodules[pin.name] = Instance("OBUFTDS",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit] o_O=p_port[bit], o_OB=n_port[bit]
@ -338,7 +338,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None, i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None) o_invert=True if invert else None)
for bit in range(len(p_port)): for bit in range(len(p_port)):
m.submodules += Instance("IOBUFDS", m.submodules[pin.name] = Instance("IOBUFDS",
i_T=t, i_T=t,
i_I=o[bit], i_I=o[bit],
o_O=i[bit], o_O=i[bit],