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back.rtlil: prepare for Yosys sigspec slicing improvements.

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See YosysHQ/yosys#741.
This commit is contained in:
whitequark 2018-12-16 18:03:14 +00:00
parent db5fd1e4c4
commit 33f32a25f5
1 changed files with 25 additions and 27 deletions
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52
nmigen/back/rtlil.py
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@ -275,6 +275,19 @@ class _ValueCompiler(xfrm.AbstractValueTransformer):
def on_Cat(self, value): def on_Cat(self, value):
return "{{ {} }}".format(" ".join(reversed([self(o) for o in value.operands]))) return "{{ {} }}".format(" ".join(reversed([self(o) for o in value.operands])))
def _prepare_value_for_Slice(self, value):
raise NotImplementedError # :nocov:
def on_Slice(self, value):
if value.start == 0 and value.end == len(value.value):
return self(value.value)
sigspec = self._prepare_value_for_Slice(value.value)
if value.start + 1 == value.end:
return "{} [{}]".format(sigspec, value.start)
else:
return "{} [{}:{}]".format(sigspec, value.end - 1, value.start)
class _RHSValueCompiler(_ValueCompiler): class _RHSValueCompiler(_ValueCompiler):
operator_map = { operator_map = {
@ -402,20 +415,15 @@ class _RHSValueCompiler(_ValueCompiler):
else: else:
raise TypeError # :nocov: raise TypeError # :nocov:
def on_Slice(self, value): def _prepare_value_for_Slice(self, value):
if value.start == 0 and value.end == len(value.value): # Uncomment after the following is merged: https://github.com/YosysHQ/yosys/pull/741
return self(value.value) # if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)):
if isinstance(value, ast.Signal):
if isinstance(value.value, ast.Signal): sigspec = self(value)
sigspec = self(value.value)
else: else:
sigspec = self.s.rtlil.wire(len(value.value)) sigspec = self.s.rtlil.wire(len(value))
self.s.rtlil.connect(sigspec, self(value.value)) self.s.rtlil.connect(sigspec, self(value))
return sigspec
if value.start + 1 == value.end:
return "{} [{}]".format(sigspec, value.start)
else:
return "{} [{}:{}]".format(sigspec, value.end - 1, value.start)
def on_Part(self, value): def on_Part(self, value):
raise NotImplementedError raise NotImplementedError
@ -437,22 +445,12 @@ class _LHSValueCompiler(_ValueCompiler):
def on_Signal(self, value): def on_Signal(self, value):
wire_curr, wire_next = self.s.resolve(value) wire_curr, wire_next = self.s.resolve(value)
if wire_next is None: if wire_next is None:
raise ValueError("Cannot return lhs for non-driven signal {}".format(repr(value))) raise ValueError("No LHS wire for non-driven signal {}".format(repr(value)))
return wire_next return wire_next
def on_Slice(self, value): def _prepare_value_for_Slice(self, value):
if value.start == 0 and value.end == len(value.value): assert isinstance(value, (ast.Signal, ast.Slice, ast.Cat))
return self(value.value) return self(value)
if isinstance(value.value, ast.Signal):
sigspec = self(value.value)
else:
raise NotImplementedError
if value.start + 1 == value.end:
return "{} [{}]".format(sigspec, value.start)
else:
return "{} [{}:{}]".format(sigspec, value.end - 1, value.start)
def on_Part(self, value): def on_Part(self, value):
raise NotImplementedError raise NotImplementedError