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hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.

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This commit is contained in:
whitequark 2018-12-26 12:42:43 +00:00
parent 934546e633
commit 35a44f017f
2 changed files with 17 additions and 12 deletions
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23
nmigen/hdl/dsl.py
View file

@ -260,17 +260,18 @@ class Module(_ModuleBuilderRoot):
@next.setter
def next(self, name):
for ctrl_name, ctrl_data in reversed(self._ctrl_stack):
if ctrl_name == "FSM":
if name not in ctrl_data["encoding"]:
ctrl_data["encoding"][name] = len(ctrl_data["encoding"])
self._add_statement(
assigns=[ctrl_data["signal"].eq(ctrl_data["encoding"][name])],
domain=ctrl_data["domain"],
depth=len(self._ctrl_stack))
break
else:
raise SyntaxError("`m.next = <...>` is only permitted inside an FSM")
if self._ctrl_context != "FSM":
for level, (ctrl_name, ctrl_data) in enumerate(reversed(self._ctrl_stack)):
if ctrl_name == "FSM":
if name not in ctrl_data["encoding"]:
ctrl_data["encoding"][name] = len(ctrl_data["encoding"])
self._add_statement(
assigns=[ctrl_data["signal"].eq(ctrl_data["encoding"][name])],
domain=ctrl_data["domain"],
depth=len(self._ctrl_stack))
return
raise SyntaxError("`m.next = <...>` is only permitted inside an FSM state")
def _pop_ctrl(self):
name, data = self._ctrl_stack.pop()

6
nmigen/test/test_hdl_dsl.py
View file

@ -392,8 +392,12 @@ class DSLTestCase(FHDLTestCase):
msg="Only assignment to `m.next` is permitted"):
m.next
with self.assertRaises(SyntaxError,
msg="`m.next = <...>` is only permitted inside an FSM"):
msg="`m.next = <...>` is only permitted inside an FSM state"):
m.next = "FOO"
with self.assertRaises(SyntaxError,
msg="`m.next = <...>` is only permitted inside an FSM state"):
with m.FSM():
m.next = "FOO"
def test_auto_pop_ctrl(self):
m = Module()