hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.

This commit is contained in:
whitequark 2018-12-26 12:42:43 +00:00
parent 934546e633
commit 35a44f017f
2 changed files with 17 additions and 12 deletions

View file

@ -260,17 +260,18 @@ class Module(_ModuleBuilderRoot):
@next.setter @next.setter
def next(self, name): def next(self, name):
for ctrl_name, ctrl_data in reversed(self._ctrl_stack): if self._ctrl_context != "FSM":
if ctrl_name == "FSM": for level, (ctrl_name, ctrl_data) in enumerate(reversed(self._ctrl_stack)):
if name not in ctrl_data["encoding"]: if ctrl_name == "FSM":
ctrl_data["encoding"][name] = len(ctrl_data["encoding"]) if name not in ctrl_data["encoding"]:
self._add_statement( ctrl_data["encoding"][name] = len(ctrl_data["encoding"])
assigns=[ctrl_data["signal"].eq(ctrl_data["encoding"][name])], self._add_statement(
domain=ctrl_data["domain"], assigns=[ctrl_data["signal"].eq(ctrl_data["encoding"][name])],
depth=len(self._ctrl_stack)) domain=ctrl_data["domain"],
break depth=len(self._ctrl_stack))
else: return
raise SyntaxError("`m.next = <...>` is only permitted inside an FSM")
raise SyntaxError("`m.next = <...>` is only permitted inside an FSM state")
def _pop_ctrl(self): def _pop_ctrl(self):
name, data = self._ctrl_stack.pop() name, data = self._ctrl_stack.pop()

View file

@ -392,8 +392,12 @@ class DSLTestCase(FHDLTestCase):
msg="Only assignment to `m.next` is permitted"): msg="Only assignment to `m.next` is permitted"):
m.next m.next
with self.assertRaises(SyntaxError, with self.assertRaises(SyntaxError,
msg="`m.next = <...>` is only permitted inside an FSM"): msg="`m.next = <...>` is only permitted inside an FSM state"):
m.next = "FOO" m.next = "FOO"
with self.assertRaises(SyntaxError,
msg="`m.next = <...>` is only permitted inside an FSM state"):
with m.FSM():
m.next = "FOO"
def test_auto_pop_ctrl(self): def test_auto_pop_ctrl(self):
m = Module() m = Module()