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hdl.ast: improve tests for exceptional conditions.

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This commit is contained in:
whitequark 2019-04-21 07:20:00 +00:00
parent 33f9bd2a1d
commit 360bc9b5b4
1 changed files with 24 additions and 12 deletions
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36
nmigen/test/test_hdl_ast.py
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@ -8,11 +8,13 @@ class ValueTestCase(FHDLTestCase):
self.assertIsInstance(Value.wrap(True), Const) self.assertIsInstance(Value.wrap(True), Const)
c = Const(0) c = Const(0)
self.assertIs(Value.wrap(c), c) self.assertIs(Value.wrap(c), c)
with self.assertRaises(TypeError): with self.assertRaises(TypeError,
msg="Object ''str'' is not an nMigen value"):
Value.wrap("str") Value.wrap("str")
def test_bool(self): def test_bool(self):
with self.assertRaises(TypeError): with self.assertRaises(TypeError,
msg="Attempted to convert nMigen value to boolean"):
if Const(0): if Const(0):
pass pass
@ -28,7 +30,8 @@ class ValueTestCase(FHDLTestCase):
self.assertIsInstance(s2, Slice) self.assertIsInstance(s2, Slice)
self.assertEqual(s2.start, 3) self.assertEqual(s2.start, 3)
self.assertEqual(s2.end, 4) self.assertEqual(s2.end, 4)
with self.assertRaises(IndexError): with self.assertRaises(IndexError,
msg="Cannot index 5 bits into 4-bit value"):
Const(10)[5] Const(10)[5]
def test_getitem_slice(self): def test_getitem_slice(self):
@ -53,7 +56,8 @@ class ValueTestCase(FHDLTestCase):
self.assertEqual(s3.parts[2].end, 5) self.assertEqual(s3.parts[2].end, 5)
def test_getitem_wrong(self): def test_getitem_wrong(self):
with self.assertRaises(TypeError): with self.assertRaises(TypeError,
msg="Cannot index value with 'str'"):
Const(31)["str"] Const(31)["str"]
@ -69,7 +73,8 @@ class ConstTestCase(FHDLTestCase):
self.assertEqual(Const(0, (0, False)).shape(), (0, False)) self.assertEqual(Const(0, (0, False)).shape(), (0, False))
def test_shape_bad(self): def test_shape_bad(self):
with self.assertRaises(TypeError): with self.assertRaises(TypeError,
msg="Width must be a non-negative integer, not '-1'"):
Const(1, -1) Const(1, -1)
def test_normalization(self): def test_normalization(self):
@ -263,18 +268,23 @@ class SliceTestCase(FHDLTestCase):
self.assertEqual((s1.start, s1.end), (4, 7)) self.assertEqual((s1.start, s1.end), (4, 7))
def test_start_end_wrong(self): def test_start_end_wrong(self):
with self.assertRaises(TypeError): with self.assertRaises(TypeError,
msg="Slice start must be an integer, not ''x''"):
Slice(0, "x", 1) Slice(0, "x", 1)
with self.assertRaises(TypeError): with self.assertRaises(TypeError,
msg="Slice end must be an integer, not ''x''"):
Slice(0, 1, "x") Slice(0, 1, "x")
def test_start_end_out_of_range(self): def test_start_end_out_of_range(self):
c = Const(0, 8) c = Const(0, 8)
with self.assertRaises(IndexError): with self.assertRaises(IndexError,
msg="Cannot start slice 10 bits into 8-bit value"):
Slice(c, 10, 12) Slice(c, 10, 12)
with self.assertRaises(IndexError): with self.assertRaises(IndexError,
msg="Cannot end slice 12 bits into 8-bit value"):
Slice(c, 0, 12) Slice(c, 0, 12)
with self.assertRaises(IndexError): with self.assertRaises(IndexError,
msg="Slice start 4 must be less than slice end 2"):
Slice(c, 4, 2) Slice(c, 4, 2)
def test_repr(self): def test_repr(self):
@ -480,7 +490,8 @@ class ClockSignalTestCase(FHDLTestCase):
s2 = ClockSignal("pix") s2 = ClockSignal("pix")
self.assertEqual(s2.domain, "pix") self.assertEqual(s2.domain, "pix")
with self.assertRaises(TypeError): with self.assertRaises(TypeError,
msg="Clock domain name must be a string, not '1'"):
ClockSignal(1) ClockSignal(1)
def test_shape(self): def test_shape(self):
@ -498,7 +509,8 @@ class ResetSignalTestCase(FHDLTestCase):
s2 = ResetSignal("pix") s2 = ResetSignal("pix")
self.assertEqual(s2.domain, "pix") self.assertEqual(s2.domain, "pix")
with self.assertRaises(TypeError): with self.assertRaises(TypeError,
msg="Clock domain name must be a string, not '1'"):
ResetSignal(1) ResetSignal(1)
def test_shape(self): def test_shape(self):