build.dsl: add Resource.family abstraction.

nmigen/build/dsl.py

@@ -181,6 +181,20 @@ class Subsignal:
 
 
 class Resource(Subsignal):
+    @classmethod
+    def family(cls, name_or_number, number=None, *, ios, default_name):
+        # This constructor accepts two different forms:
+        #  1. Number-only form:
+        #       Resource.family(0, default_name="name", ios=[Pins("A0 A1")])
+        #  2. Name-and-number (name override) form:
+        #       Resource.family("override", 0, default_name="name", ios=...)
+        # This makes it easier to build abstractions for resources, e.g. an SPIResource abstraction
+        # could simply delegate to `Resource.family(*args, default_name="spi", ios=ios)`.
+        if number is None: # name_or_number is number
+            return cls(default_name, name_or_number, *ios)
+        else: # name_or_number is name
+            return cls(name_or_number, number, *ios)
+
     def __init__(self, name, number, *args):
         super().__init__(name, *args)
 

nmigen/test/test_build_dsl.py

@@ -225,6 +225,15 @@ class ResourceTestCase(FHDLTestCase):
                                   " (subsignal rx (pins i A1))"
                                   " (attrs IOSTANDARD=LVCMOS33))")
 
+    def test_family(self):
+        ios = [Subsignal("clk", Pins("A0", dir="o"))]
+        r1  = Resource.family(0, default_name="spi", ios=ios)
+        r2  = Resource.family("spi_flash", 0, default_name="spi", ios=ios)
+        self.assertEqual(r1.name, "spi")
+        self.assertEqual(r1.ios, ios)
+        self.assertEqual(r2.name, "spi_flash")
+        self.assertEqual(r2.ios, ios)
+
 
 class ConnectorTestCase(FHDLTestCase):
     def test_string(self):