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build.dsl: add Resource.family abstraction.

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This commit is contained in:
whitequark 2019-07-09 02:44:03 +00:00
parent 7b4fbf8e01
commit 367ad5aee7
2 changed files with 23 additions and 0 deletions
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9
nmigen/test/test_build_dsl.py
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@ -225,6 +225,15 @@ class ResourceTestCase(FHDLTestCase):
" (subsignal rx (pins i A1))"
" (attrs IOSTANDARD=LVCMOS33))")
def test_family(self):
ios = [Subsignal("clk", Pins("A0", dir="o"))]
r1 = Resource.family(0, default_name="spi", ios=ios)
r2 = Resource.family("spi_flash", 0, default_name="spi", ios=ios)
self.assertEqual(r1.name, "spi")
self.assertEqual(r1.ios, ios)
self.assertEqual(r2.name, "spi_flash")
self.assertEqual(r2.ios, ios)
class ConnectorTestCase(FHDLTestCase):
def test_string(self):