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build.dsl: add Resource.family abstraction.

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This commit is contained in:
whitequark 2019-07-09 02:44:03 +00:00
parent 7b4fbf8e01
commit 367ad5aee7
2 changed files with 23 additions and 0 deletions
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14
nmigen/build/dsl.py
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@ -181,6 +181,20 @@ class Subsignal:
class Resource(Subsignal): class Resource(Subsignal):
@classmethod
def family(cls, name_or_number, number=None, *, ios, default_name):
# This constructor accepts two different forms:
# 1. Number-only form:
# Resource.family(0, default_name="name", ios=[Pins("A0 A1")])
# 2. Name-and-number (name override) form:
# Resource.family("override", 0, default_name="name", ios=...)
# This makes it easier to build abstractions for resources, e.g. an SPIResource abstraction
# could simply delegate to `Resource.family(*args, default_name="spi", ios=ios)`.
if number is None: # name_or_number is number
return cls(default_name, name_or_number, *ios)
else: # name_or_number is name
return cls(name_or_number, number, *ios)
def __init__(self, name, number, *args): def __init__(self, name, number, *args):
super().__init__(name, *args) super().__init__(name, *args)

9
nmigen/test/test_build_dsl.py
View file

@ -225,6 +225,15 @@ class ResourceTestCase(FHDLTestCase):
" (subsignal rx (pins i A1))" " (subsignal rx (pins i A1))"
" (attrs IOSTANDARD=LVCMOS33))") " (attrs IOSTANDARD=LVCMOS33))")
def test_family(self):
ios = [Subsignal("clk", Pins("A0", dir="o"))]
r1 = Resource.family(0, default_name="spi", ios=ios)
r2 = Resource.family("spi_flash", 0, default_name="spi", ios=ios)
self.assertEqual(r1.name, "spi")
self.assertEqual(r1.ios, ios)
self.assertEqual(r2.name, "spi_flash")
self.assertEqual(r2.ios, ios)
class ConnectorTestCase(FHDLTestCase): class ConnectorTestCase(FHDLTestCase):
def test_string(self): def test_string(self):