usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity

back.rtlil: always initialize the entire memory.

Browse source 
This avoids reading 'x from the memory in simulation. In general,
FPGA memories can only be initialized in block granularity, and
zero-initializing is cheap, so this is not a significant issue with
resource consumption.
This commit is contained in:
whitequark 2018-12-22 05:27:42 +00:00
parent 99b778158d
commit 37b81309d3
1 changed files with 5 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
nmigen/back/rtlil.py
View file

@ -624,7 +624,11 @@ def convert_fragment(builder, fragment, name, top):
memories[memory] = module.memory(width=memory.width, size=memory.depth, memories[memory] = module.memory(width=memory.width, size=memory.depth,
name=memory.name) name=memory.name)
addr_bits = bits_for(memory.depth) addr_bits = bits_for(memory.depth)
for addr, data in enumerate(memory.init): for addr in range(memory.depth):
if addr < len(memory.init):
data = memory.init[addr]
else:
data = 0
module.cell("$meminit", ports={ module.cell("$meminit", ports={
"\\ADDR": rhs_compiler(ast.Const(addr, addr_bits)), "\\ADDR": rhs_compiler(ast.Const(addr, addr_bits)),
"\\DATA": rhs_compiler(ast.Const(data, memory.width)), "\\DATA": rhs_compiler(ast.Const(data, memory.width)),