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hdl.ir: during port propagation, defs should take priority over uses.

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This commit is contained in:
whitequark 2019-05-13 15:34:13 +00:00
parent 921f506e69
commit 39bc59c924
2 changed files with 27 additions and 5 deletions
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11
nmigen/hdl/ir.py
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@ -445,11 +445,6 @@ class Fragment:
for sig in uses:
if sig in defs:
lca = reduce(lca_of, uses[sig], defs[sig])
frag = defs[sig]
while frag != lca:
frag.add_ports(sig, dir="o")
frag = parent[frag]
else:
lca = reduce(lca_of, uses[sig])
@ -460,6 +455,12 @@ class Fragment:
frag.add_ports(sig, dir="i")
frag = parent[frag]
if sig in defs:
frag = defs[sig]
while frag != lca:
frag.add_ports(sig, dir="o")
frag = parent[frag]
for sig in ios:
frag = ios[sig]
while frag is not None:

21
nmigen/test/test_hdl_ir.py
View file

@ -156,6 +156,27 @@ class FragmentPortsTestCase(FHDLTestCase):
(self.c2, "o"),
]))
def test_output_from_subfragment_2(self):
f1 = Fragment()
f1.add_statements(
self.c1.eq(self.s1)
)
f2 = Fragment()
f2.add_statements(
self.c2.eq(self.s1)
)
f1.add_subfragment(f2)
f3 = Fragment()
f3.add_statements(
self.s1.eq(0)
)
f2.add_subfragment(f3)
f1._propagate_ports(ports=(), all_undef_as_ports=True)
self.assertEqual(f2.ports, SignalDict([
(self.s1, "o"),
]))
def test_input_output_sibling(self):
f1 = Fragment()
f2 = Fragment()