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back.rtlil: it is not necessary to match binop operand width.

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whitequark 2019-10-02 03:38:58 +00:00
parent 905920aa76
commit 3a1dae591b
1 changed files with 0 additions and 1 deletions
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nmigen/back/rtlil.py
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@ -490,7 +490,6 @@ class _RHSValueCompiler(_ValueCompiler):
rhs_wire = self(rhs) rhs_wire = self(rhs)
else: else:
lhs_sign = rhs_sign = True lhs_sign = rhs_sign = True
lhs_bits = rhs_bits = max(lhs_bits, rhs_bits)
lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign) lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign) rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
res_bits, res_sign = value.shape() res_bits, res_sign = value.shape()