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back.pysim: implement "sync processes", like migen.sim generators.

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This commit is contained in:
whitequark 2018-12-14 05:13:58 +00:00
parent d791b77cc8
commit 3bb7a87e0f
2 changed files with 20 additions and 9 deletions
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15
examples/ctrl.py
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@ -23,11 +23,12 @@ print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
sim = pysim.Simulator(frag, vcd_file=open("ctrl.vcd", "w"))
sim.add_clock("sync", 1e-6)
def sim_proc():
yield pysim.Delay(15.25e-6)
yield ctr.ce.eq(Const(1))
yield pysim.Delay(15.25e-6)
yield pysim.Tick("sync")
yield ctr.ce.eq(Const(0))
sim.add_process(sim_proc())
def ce_proc():
yield; yield; yield
yield ctr.ce.eq(1)
yield; yield; yield
yield ctr.ce.eq(0)
yield; yield; yield
yield ctr.ce.eq(1)
sim.add_sync_process(ce_proc())
with sim: sim.run_until(100e-6, run_passive=True)