back.pysim: implement "sync processes", like migen.sim generators.

examples/ctrl.py

@@ -23,11 +23,12 @@ print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
 
 sim = pysim.Simulator(frag, vcd_file=open("ctrl.vcd", "w"))
 sim.add_clock("sync", 1e-6)
-def sim_proc():
-    yield pysim.Delay(15.25e-6)
-    yield ctr.ce.eq(Const(1))
-    yield pysim.Delay(15.25e-6)
-    yield pysim.Tick("sync")
-    yield ctr.ce.eq(Const(0))
-sim.add_process(sim_proc())
+def ce_proc():
+    yield; yield; yield
+    yield ctr.ce.eq(1)
+    yield; yield; yield
+    yield ctr.ce.eq(0)
+    yield; yield; yield
+    yield ctr.ce.eq(1)
+sim.add_sync_process(ce_proc())
 with sim: sim.run_until(100e-6, run_passive=True)

nmigen/back/pysim.py

@@ -223,8 +223,8 @@ class Simulator:
         for subfragment, name in fragment.subfragments:
             self._add_fragment(subfragment, (*hierarchy, name))
 
-    def add_process(self, fn):
-        self._processes.add(fn)
+    def add_process(self, process):
+        self._processes.add(process)
 
     def add_clock(self, domain, period):
         clk = self._domains[domain].clk
@@ -238,6 +238,16 @@ class Simulator:
                 yield Delay(half_period)
         self.add_process(clk_process())
 
+    def add_sync_process(self, process, domain="sync"):
+        def sync_process():
+            try:
+                result = process.send(None)
+                while True:
+                    result = process.send((yield (result or Tick(domain))))
+            except StopIteration:
+                pass
+        self.add_process(sync_process())
+
     def _signal_name_in_fragment(self, fragment, signal):
         for subfragment, name in fragment.subfragments:
             if signal in subfragment.ports: