examples: reorganize into examples/basic and examples/board.

examples/basic/alu.py

@@ -0,0 +1,28 @@
+from nmigen import *
+from nmigen.cli import main
+
+
+class ALU(Elaboratable):
+    def __init__(self, width):
+        self.sel = Signal(2)
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+        self.co  = Signal()
+
+    def elaborate(self, platform):
+        m = Module()
+        with m.If(self.sel == 0b00):
+            m.d.comb += self.o.eq(self.a | self.b)
+        with m.Elif(self.sel == 0b01):
+            m.d.comb += self.o.eq(self.a & self.b)
+        with m.Elif(self.sel == 0b10):
+            m.d.comb += self.o.eq(self.a ^ self.b)
+        with m.Else():
+            m.d.comb += Cat(self.o, self.co).eq(self.a - self.b)
+        return m
+
+
+if __name__ == "__main__":
+    alu = ALU(width=16)
+    main(alu, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co])

examples/basic/alu_hier.py

@@ -0,0 +1,58 @@
+from nmigen import *
+from nmigen.cli import main
+
+
+class Adder(Elaboratable):
+    def __init__(self, width):
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.comb += self.o.eq(self.a + self.b)
+        return m
+
+
+class Subtractor(Elaboratable):
+    def __init__(self, width):
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.comb += self.o.eq(self.a - self.b)
+        return m
+
+
+class ALU(Elaboratable):
+    def __init__(self, width):
+        self.op  = Signal()
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+
+        self.add = Adder(width)
+        self.sub = Subtractor(width)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.add = self.add
+        m.submodules.sub = self.sub
+        m.d.comb += [
+            self.add.a.eq(self.a),
+            self.sub.a.eq(self.a),
+            self.add.b.eq(self.b),
+            self.sub.b.eq(self.b),
+        ]
+        with m.If(self.op):
+            m.d.comb += self.o.eq(self.sub.o)
+        with m.Else():
+            m.d.comb += self.o.eq(self.add.o)
+        return m
+
+
+if __name__ == "__main__":
+    alu = ALU(width=16)
+    main(alu, ports=[alu.op, alu.a, alu.b, alu.o])

examples/basic/arst.py

@@ -0,0 +1,21 @@
+from nmigen import *
+from nmigen.cli import main
+
+
+class ClockDivisor(Elaboratable):
+    def __init__(self, factor):
+        self.v = Signal(factor)
+        self.o = Signal()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.sync += self.v.eq(self.v + 1)
+        m.d.comb += self.o.eq(self.v[-1])
+        return m
+
+
+if __name__ == "__main__":
+    ctr = ClockDivisor(factor=16)
+    m = ctr.elaborate(platform=None)
+    m.domains += ClockDomain("sync", async_reset=True)
+    main(m, ports=[ctr.o])

examples/basic/cdc.py

@@ -0,0 +1,10 @@
+from nmigen import *
+from nmigen.cli import main
+
+
+i, o = Signal(name="i"), Signal(name="o")
+m = Module()
+m.submodules += MultiReg(i, o)
+
+if __name__ == "__main__":
+    main(m, ports=[i, o])

examples/basic/ctr.py

@@ -0,0 +1,19 @@
+from nmigen import *
+from nmigen.cli import main, pysim
+
+
+class Counter(Elaboratable):
+    def __init__(self, width):
+        self.v = Signal(width, reset=2**width-1)
+        self.o = Signal()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.sync += self.v.eq(self.v + 1)
+        m.d.comb += self.o.eq(self.v[-1])
+        return m
+
+
+ctr = Counter(width=16)
+if __name__ == "__main__":
+    main(ctr, ports=[ctr.o])

examples/basic/ctr_ce.py

@@ -0,0 +1,35 @@
+from nmigen import *
+from nmigen.back import rtlil, verilog, pysim
+
+
+class Counter(Elaboratable):
+    def __init__(self, width):
+        self.v = Signal(width, reset=2**width-1)
+        self.o = Signal()
+        self.ce = Signal()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.sync += self.v.eq(self.v + 1)
+        m.d.comb += self.o.eq(self.v[-1])
+        return CEInserter(self.ce)(m.lower(platform))
+
+
+ctr = Counter(width=16)
+
+print(verilog.convert(ctr, ports=[ctr.o, ctr.ce]))
+
+with pysim.Simulator(ctr,
+        vcd_file=open("ctrl.vcd", "w"),
+        gtkw_file=open("ctrl.gtkw", "w"),
+        traces=[ctr.ce, ctr.v, ctr.o]) as sim:
+    sim.add_clock(1e-6)
+    def ce_proc():
+        yield; yield; yield
+        yield ctr.ce.eq(1)
+        yield; yield; yield
+        yield ctr.ce.eq(0)
+        yield; yield; yield
+        yield ctr.ce.eq(1)
+    sim.add_sync_process(ce_proc())
+    sim.run_until(100e-6, run_passive=True)

examples/basic/fsm.py

@@ -0,0 +1,64 @@
+from nmigen import *
+from nmigen.cli import main
+
+
+class UARTReceiver(Elaboratable):
+    def __init__(self, divisor):
+        self.divisor = divisor
+
+        self.i    = Signal()
+        self.data = Signal(8)
+        self.rdy  = Signal()
+        self.ack  = Signal()
+        self.err  = Signal()
+
+    def elaborate(self, platform):
+        m = Module()
+
+        ctr = Signal(max=self.divisor)
+        stb = Signal()
+        with m.If(ctr == 0):
+            m.d.sync += ctr.eq(self.divisor - 1)
+            m.d.comb += stb.eq(1)
+        with m.Else():
+            m.d.sync += ctr.eq(ctr - 1)
+
+        bit = Signal(3)
+        with m.FSM() as fsm:
+            with m.State("START"):
+                with m.If(~self.i):
+                    m.next = "DATA"
+                    m.d.sync += [
+                        ctr.eq(self.divisor // 2),
+                        bit.eq(7),
+                    ]
+            with m.State("DATA"):
+                with m.If(stb):
+                    m.d.sync += [
+                        bit.eq(bit - 1),
+                        self.data.eq(Cat(self.i, self.data))
+                    ]
+                    with m.If(bit == 0):
+                        m.next = "STOP"
+            with m.State("STOP"):
+                with m.If(stb):
+                    with m.If(self.i):
+                        m.next = "DONE"
+                    with m.Else():
+                        m.next = "ERROR"
+
+            with m.State("DONE"):
+                m.d.comb += self.rdy.eq(1)
+                with m.If(self.ack):
+                    m.next = "START"
+
+            m.d.comb += self.err.eq(fsm.ongoing("ERROR"))
+            with m.State("ERROR"):
+                pass
+
+        return m
+
+
+if __name__ == "__main__":
+    rx = UARTReceiver(20)
+    main(rx, ports=[rx.i, rx.data, rx.rdy, rx.ack, rx.err])

examples/basic/gpio.py

@@ -0,0 +1,28 @@
+from types import SimpleNamespace
+from nmigen import *
+from nmigen.cli import main
+
+
+class GPIO(Elaboratable):
+    def __init__(self, pins, bus):
+        self.pins = pins
+        self.bus  = bus
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.comb += self.bus.r_data.eq(self.pins[self.bus.addr])
+        with m.If(self.bus.we):
+            m.d.sync += self.pins[self.bus.addr].eq(self.bus.w_data)
+        return m
+
+
+if __name__ == "__main__":
+    bus = Record([
+        ("addr",   3),
+        ("r_data", 1),
+        ("w_data", 1),
+        ("we",     1),
+    ])
+    pins = Signal(8)
+    gpio = GPIO(Array(pins), bus)
+    main(gpio, ports=[pins, bus.addr, bus.r_data, bus.w_data, bus.we])

examples/basic/inst.py

@@ -0,0 +1,26 @@
+from nmigen import *
+from nmigen.cli import main
+
+
+class System(Elaboratable):
+    def __init__(self):
+        self.adr   = Signal(16)
+        self.dat_r = Signal(8)
+        self.dat_w = Signal(8)
+        self.we    = Signal()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.cpu = Instance("CPU",
+            p_RESET_ADDR=0xfff0,
+            i_d_adr  =self.adr,
+            i_d_dat_r=self.dat_r,
+            o_d_dat_w=self.dat_w,
+            i_d_we   =self.we,
+        )
+        return m
+
+
+if __name__ == "__main__":
+    sys = System()
+    main(sys, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we])

examples/basic/mem.py

@@ -0,0 +1,29 @@
+from nmigen import *
+from nmigen.cli import main
+
+
+class RegisterFile(Elaboratable):
+    def __init__(self):
+        self.adr   = Signal(4)
+        self.dat_r = Signal(8)
+        self.dat_w = Signal(8)
+        self.we    = Signal()
+        self.mem   = Memory(width=8, depth=16, init=[0xaa, 0x55])
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.rdport = rdport = self.mem.read_port()
+        m.submodules.wrport = wrport = self.mem.write_port()
+        m.d.comb += [
+            rdport.addr.eq(self.adr),
+            self.dat_r.eq(rdport.data),
+            wrport.addr.eq(self.adr),
+            wrport.data.eq(self.dat_w),
+            wrport.en.eq(self.we),
+        ]
+        return m
+
+
+if __name__ == "__main__":
+    rf = RegisterFile()
+    main(rf, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we])

examples/basic/pmux.py

@@ -0,0 +1,29 @@
+from nmigen import *
+from nmigen.cli import main
+
+
+class ParMux(Elaboratable):
+    def __init__(self, width):
+        self.s = Signal(3)
+        self.a = Signal(width)
+        self.b = Signal(width)
+        self.c = Signal(width)
+        self.o = Signal(width)
+
+    def elaborate(self, platform):
+        m = Module()
+        with m.Switch(self.s):
+            with m.Case("--1"):
+                m.d.comb += self.o.eq(self.a)
+            with m.Case("-1-"):
+                m.d.comb += self.o.eq(self.b)
+            with m.Case("1--"):
+                m.d.comb += self.o.eq(self.c)
+            with m.Case():
+                m.d.comb += self.o.eq(0)
+        return m
+
+
+if __name__ == "__main__":
+    pmux = ParMux(width=16)
+    main(pmux, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o])

examples/basic/por.py

@@ -0,0 +1,19 @@
+from nmigen import *
+from nmigen.cli import main
+
+
+m = Module()
+cd_por  = ClockDomain(reset_less=True)
+cd_sync = ClockDomain()
+m.domains += cd_por, cd_sync
+
+delay = Signal(max=255, reset=255)
+with m.If(delay != 0):
+    m.d.por += delay.eq(delay - 1)
+m.d.comb += [
+    ClockSignal().eq(cd_por.clk),
+    ResetSignal().eq(delay != 0),
+]
+
+if __name__ == "__main__":
+    main(m, ports=[cd_por.clk])