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hdl.dsl: reject name mismatch in m.domains.<name> +=.

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This would violate invariants later in the elaboration process.

Fixes #282.
This commit is contained in:
whitequark 2020-02-06 16:13:59 +00:00
parent 86b57fe6b6
commit 3df429703c
2 changed files with 10 additions and 0 deletions
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4
nmigen/hdl/dsl.py
View file

@ -118,6 +118,10 @@ class _ModuleBuilderDomainSet:
if not isinstance(domain, ClockDomain): if not isinstance(domain, ClockDomain):
raise TypeError("Only clock domains may be added to `m.domains`, not {!r}" raise TypeError("Only clock domains may be added to `m.domains`, not {!r}"
.format(domain)) .format(domain))
if domain.name != name:
raise NameError("Clock domain name {!r} must match name in `m.domains.{} += ...` "
"syntax"
.format(domain.name, name))
self._builder._add_domain(domain) self._builder._add_domain(domain)

6
nmigen/test/test_hdl_dsl.py
View file

@ -716,6 +716,12 @@ class DSLTestCase(FHDLTestCase):
msg="Only clock domains may be added to `m.domains`, not 1"): msg="Only clock domains may be added to `m.domains`, not 1"):
m.domains += 1 m.domains += 1
def test_domain_add_wrong_name(self):
m = Module()
with self.assertRaises(NameError,
msg="Clock domain name 'bar' must match name in `m.domains.foo += ...` syntax"):
m.domains.foo = ClockDomain("bar")
def test_lower(self): def test_lower(self):
m1 = Module() m1 = Module()
m1.d.comb += self.c1.eq(self.s1) m1.d.comb += self.c1.eq(self.s1)