lib.coding: fix tests to actually run, and fix code to fix tests.
This commit is contained in:
		
							parent
							
								
									470d66934f
								
							
						
					
					
						commit
						3ea35b8566
					
				|  | @ -69,7 +69,7 @@ class PriorityEncoder: | |||
|         m = Module() | ||||
|         for j, b in enumerate(reversed(self.i)): | ||||
|             with m.If(b): | ||||
|                 m.d.comb += self.o.eq(j) | ||||
|                 m.d.comb += self.o.eq(len(self.i) - j - 1) | ||||
|         m.d.comb += self.n.eq(self.i == 0) | ||||
|         return m.lower(platform) | ||||
| 
 | ||||
|  | @ -105,9 +105,8 @@ class Decoder: | |||
|             for j in range(len(self.o)): | ||||
|                 with m.Case(j): | ||||
|                     m.d.comb += self.o.eq(1 << j) | ||||
|             with m.Case(): | ||||
|                 with m.If(self.n): | ||||
|                     m.d.comb += self.o.eq(0) | ||||
|         with m.If(self.n): | ||||
|             m.d.comb += self.o.eq(0) | ||||
|         return m.lower(platform) | ||||
| 
 | ||||
| 
 | ||||
|  |  | |||
|  | @ -28,6 +28,7 @@ class EncoderTestCase(FHDLTestCase): | |||
|                 self.assertEqual((yield enc.o), 0) | ||||
| 
 | ||||
|             sim.add_process(process) | ||||
|             sim.run() | ||||
| 
 | ||||
| 
 | ||||
| class PriorityEncoderTestCase(FHDLTestCase): | ||||
|  | @ -54,6 +55,7 @@ class PriorityEncoderTestCase(FHDLTestCase): | |||
|                 self.assertEqual((yield enc.o), 1) | ||||
| 
 | ||||
|             sim.add_process(process) | ||||
|             sim.run() | ||||
| 
 | ||||
| 
 | ||||
| class DecoderTestCase(FHDLTestCase): | ||||
|  | @ -61,18 +63,19 @@ class DecoderTestCase(FHDLTestCase): | |||
|         dec = Decoder(4) | ||||
|         with Simulator(dec) as sim: | ||||
|             def process(): | ||||
|                 self.assertEqual((yield enc.o), 0b0001) | ||||
|                 self.assertEqual((yield dec.o), 0b0001) | ||||
| 
 | ||||
|                 yield enc.i.eq(1) | ||||
|                 yield dec.i.eq(1) | ||||
|                 yield Delay() | ||||
|                 self.assertEqual((yield enc.o), 0b0010) | ||||
|                 self.assertEqual((yield dec.o), 0b0010) | ||||
| 
 | ||||
|                 yield enc.i.eq(3) | ||||
|                 yield dec.i.eq(3) | ||||
|                 yield Delay() | ||||
|                 self.assertEqual((yield enc.o), 0b1000) | ||||
|                 self.assertEqual((yield dec.o), 0b1000) | ||||
| 
 | ||||
|                 yield enc.n.eq(1) | ||||
|                 yield dec.n.eq(1) | ||||
|                 yield Delay() | ||||
|                 self.assertEqual((yield enc.o), 0b0000) | ||||
|                 self.assertEqual((yield dec.o), 0b0000) | ||||
| 
 | ||||
|             sim.add_process(process) | ||||
|             sim.run() | ||||
|  |  | |||
		Loading…
	
		Reference in a new issue
	
	 whitequark
						whitequark