hdl.dsl: add Default(), an alias for Case() with no arguments.

Fixes #197.
This commit is contained in:
whitequark 2019-09-08 12:24:18 +00:00
parent eb04a2509e
commit 3f6abc0b7a
2 changed files with 21 additions and 1 deletions

View file

@ -289,6 +289,9 @@ class Module(_ModuleBuilderRoot, Elaboratable):
self._ctrl_context = "Switch"
self._statements = _outer_case
def Default(self):
return self.Case()
@contextmanager
def FSM(self, reset=None, domain="sync", name="fsm"):
self._check_context("FSM", context=None)

View file

@ -307,7 +307,7 @@ class DSLTestCase(FHDLTestCase):
)
""")
def test_Switch_default(self):
def test_Switch_default_Case(self):
m = Module()
with m.Switch(self.w1):
with m.Case(3):
@ -324,6 +324,23 @@ class DSLTestCase(FHDLTestCase):
)
""")
def test_Switch_default_Default(self):
m = Module()
with m.Switch(self.w1):
with m.Case(3):
m.d.comb += self.c1.eq(1)
with m.Default():
m.d.comb += self.c2.eq(1)
m._flush()
self.assertRepr(m._statements, """
(
(switch (sig w1)
(case 0011 (eq (sig c1) (const 1'd1)))
(default (eq (sig c2) (const 1'd1)))
)
)
""")
def test_Switch_const_test(self):
m = Module()
with m.Switch(1):