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vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly.

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Do this to make sure all buffers, tristate/differential or not, are
instantiated the exact same way, and are subject to the same set of
toolchain bugs, if any.
This commit is contained in:
whitequark 2019-06-15 16:07:40 +00:00
parent 2a8e7bc6f2
commit 3fc5f170e6
2 changed files with 20 additions and 4 deletions
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12
nmigen/vendor/xilinx_7series.py vendored
View file

@ -234,7 +234,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
valid_xdrs=(0, 1, 2), valid_attrs=True) valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
m.d.comb += i.eq(port) for bit in range(len(port)):
m.submodules += Instance("IBUF",
i_I=port[bit],
o_O=i[bit]
)
return m return m
def get_output(self, pin, port, attrs, invert): def get_output(self, pin, port, attrs, invert):
@ -242,7 +246,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
valid_xdrs=(0, 1, 2), valid_attrs=True) valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
m.d.comb += port.eq(o) for bit in range(len(port)):
m.submodules += Instance("OBUF",
i_I=o[bit],
o_O=port[bit]
)
return m return m
def get_tristate(self, pin, port, attrs, invert): def get_tristate(self, pin, port, attrs, invert):

12
nmigen/vendor/xilinx_spartan6.py vendored
View file

@ -249,7 +249,11 @@ class XilinxSpartan6Platform(TemplatedPlatform):
valid_xdrs=(0, 1, 2), valid_attrs=True) valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
m.d.comb += i.eq(port) for bit in range(len(port)):
m.submodules += Instance("IBUF",
i_I=port[bit],
o_O=i[bit]
)
return m return m
def get_output(self, pin, port, attrs, invert): def get_output(self, pin, port, attrs, invert):
@ -257,7 +261,11 @@ class XilinxSpartan6Platform(TemplatedPlatform):
valid_xdrs=(0, 1, 2), valid_attrs=True) valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module() m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None) i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
m.d.comb += port.eq(o) for bit in range(len(port)):
m.submodules += Instance("OBUF",
i_I=o[bit],
o_O=port[bit]
)
return m return m
def get_tristate(self, pin, port, attrs, invert): def get_tristate(self, pin, port, attrs, invert):