Implement RFC 27 amendment: deprecate add_sync_process, not add_process.
This commit is contained in:
Wanda
Catherine
parent
2d42d649ee
commit
4014f6429c
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@ -80,7 +80,6 @@ class Simulator:
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.format(process))
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return process
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@deprecated("The `add_process` method is deprecated per RFC 27. Use `add_testbench` instead.")
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def add_process(self, process):
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process = self._check_process(process)
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def wrapper():
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@ -89,6 +88,7 @@ class Simulator:
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yield from process()
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self._engine.add_coroutine_process(wrapper, default_cmd=None)
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@deprecated("The `add_sync_process` method is deprecated per RFC 47. Use `add_process` or `add_testbench` instead.")
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def add_sync_process(self, process, *, domain="sync"):
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process = self._check_process(process)
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def wrapper():
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@ -107,25 +107,6 @@ class Simulator:
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except StopIteration:
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break
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try:
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if isinstance(command, (Settle, Delay, Tick)):
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frame = generator.gi_frame
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module_globals = frame.f_globals
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if '__name__' in module_globals:
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module = module_globals['__name__']
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else:
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module = "<string>"
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# If the warning action is "error", this call will throw the warning, and
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# the try block will redirect it into the generator.
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warnings.warn_explicit(
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f"Using `{command.__class__.__name__}` is deprecated within "
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f"`add_sync_process` per RFC 27; use `add_testbench` instead.",
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DeprecationWarning,
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filename=frame.f_code.co_filename,
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lineno=frame.f_lineno,
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module=module,
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registry=module_globals.setdefault("__warningregistry__", {}),
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module_globals=module_globals,
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)
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result = yield command
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exception = None
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except Exception as e:
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@ -29,9 +29,8 @@ Apply the following changes to code written against Amaranth 0.4 to migrate it t
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* Replace uses of ``Value.matches()`` with no patterns with ``Const(1)``
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* Update uses of ``amaranth.utils.log2_int(need_pow2=False)`` to :func:`amaranth.utils.ceil_log2`
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* Update uses of ``amaranth.utils.log2_int(need_pow2=True)`` to :func:`amaranth.utils.exact_log2`
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* Update uses of ``Simulator.add_process`` to ``Simulator.add_testbench``
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* Convert uses of ``Simulator.add_sync_process`` used as testbenches to ``Simulator.add_testbench``
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* Convert uses of ``yield Tick()`` within remaining ``Simulator.add_sync_process`` to plain ``yield``
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* Convert other uses of ``Simulator.add_sync_process`` to ``Simulator.add_process``
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Implemented RFCs
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@ -81,7 +80,7 @@ Toolchain changes
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* Added: ``Simulator.add_testbench``. (`RFC 27`_)
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* Deprecated: ``Settle`` simulation command. (`RFC 27`_)
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* Deprecated: ``Simulator.add_process``. (`RFC 27`_)
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* Deprecated: ``Simulator.add_sync_process``. (`RFC 27`_)
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* Removed: (deprecated in 0.4) use of mixed-case toolchain environment variable names, such as ``NMIGEN_ENV_Diamond`` or ``AMARANTH_ENV_Diamond``; use upper-case environment variable names, such as ``AMARANTH_ENV_DIAMOND``.
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@ -23,12 +23,12 @@ print(verilog.convert(ctr, ports=[ctr.o, ctr.en]))
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sim = Simulator(ctr)
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sim.add_clock(1e-6)
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def ce_proc():
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yield; yield; yield
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yield Tick(); yield Tick(); yield Tick()
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yield ctr.en.eq(1)
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yield; yield; yield
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yield Tick(); yield Tick(); yield Tick()
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yield ctr.en.eq(0)
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yield; yield; yield
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yield Tick(); yield Tick(); yield Tick()
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yield ctr.en.eq(1)
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sim.add_sync_process(ce_proc)
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sim.add_testbench(ce_proc)
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with sim.write_vcd("ctrl.vcd", "ctrl.gtkw", traces=[ctr.en, ctr.v, ctr.o]):
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sim.run_until(100e-6, run_passive=True)
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@ -26,13 +26,13 @@ class FFSynchronizerTestCase(FHDLTestCase):
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def process():
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self.assertEqual((yield o), 0)
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yield i.eq(1)
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yield
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yield Tick()
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self.assertEqual((yield o), 0)
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yield
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yield Tick()
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self.assertEqual((yield o), 0)
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yield
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yield Tick()
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self.assertEqual((yield o), 1)
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sim.add_sync_process(process)
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sim.add_process(process)
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sim.run()
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def test_reset_value(self):
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@ -45,13 +45,13 @@ class FFSynchronizerTestCase(FHDLTestCase):
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def process():
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self.assertEqual((yield o), 1)
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yield i.eq(0)
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yield
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yield Tick()
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self.assertEqual((yield o), 1)
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yield
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yield Tick()
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self.assertEqual((yield o), 1)
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yield
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yield Tick()
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self.assertEqual((yield o), 0)
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sim.add_sync_process(process)
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sim.add_process(process)
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sim.run()
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@ -221,17 +221,17 @@ class PulseSynchronizerTestCase(FHDLTestCase):
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yield ps.i.eq(0)
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# TODO: think about reset
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for n in range(5):
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yield
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yield Tick()
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# Make sure no pulses are generated in quiescent state
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for n in range(3):
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yield
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yield Tick()
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self.assertEqual((yield ps.o), 0)
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# Check conservation of pulses
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accum = 0
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for n in range(10):
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yield ps.i.eq(1 if n < 4 else 0)
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yield
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yield Tick()
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accum += yield ps.o
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self.assertEqual(accum, 4)
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sim.add_sync_process(process)
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sim.add_process(process)
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sim.run()
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@ -243,13 +243,13 @@ class CRCTestCase(unittest.TestCase):
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yield crc.start.eq(word == b"1")
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yield crc.data.eq(word)
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yield crc.valid.eq(1)
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yield
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yield Tick()
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yield crc.valid.eq(0)
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yield
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yield Tick()
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self.assertEqual((yield crc.crc), check)
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sim = Simulator(crc)
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sim.add_sync_process(process)
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sim.add_testbench(process)
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sim.add_clock(1e-6)
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sim.run()
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@ -283,18 +283,18 @@ class CRCTestCase(unittest.TestCase):
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def process():
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yield crc.start.eq(1)
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yield
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yield Tick()
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yield crc.start.eq(0)
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for word in words:
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yield crc.data.eq(word)
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yield crc.valid.eq(1)
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yield
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yield Tick()
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yield crc.valid.eq(0)
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yield
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yield Tick()
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self.assertEqual((yield crc.crc), check)
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sim = Simulator(crc)
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sim.add_sync_process(process)
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sim.add_testbench(process)
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sim.add_clock(1e-6)
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sim.run()
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@ -334,17 +334,17 @@ class CRCTestCase(unittest.TestCase):
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def process():
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yield crc.start.eq(1)
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yield
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yield Tick()
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yield crc.start.eq(0)
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for word in words:
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yield crc.data.eq(word)
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yield crc.valid.eq(1)
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yield
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yield Tick()
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yield crc.valid.eq(0)
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yield
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yield Tick()
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self.assertTrue((yield crc.match_detected))
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sim = Simulator(crc)
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sim.add_sync_process(process)
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sim.add_testbench(process)
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sim.add_clock(1e-6)
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sim.run()
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@ -325,7 +325,7 @@ class AsyncFIFOSimCase(FHDLTestCase):
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for i in range(10):
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yield fifo.w_data.eq(i)
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yield fifo.w_en.eq(1)
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yield
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yield Tick()
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if (i - ff_syncronizer_latency) > 0:
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self.assertEqual((yield fifo.r_level), i - ff_syncronizer_latency)
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@ -334,7 +334,7 @@ class AsyncFIFOSimCase(FHDLTestCase):
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simulator = Simulator(fifo)
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simulator.add_clock(100e-6)
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simulator.add_sync_process(testbench)
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simulator.add_process(testbench)
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simulator.run()
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def check_async_fifo_level(self, fifo, fill_in, expected_level, read=False):
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@ -344,10 +344,9 @@ class AsyncFIFOSimCase(FHDLTestCase):
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for i in range(fill_in):
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yield fifo.w_data.eq(i)
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yield fifo.w_en.eq(1)
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yield
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yield Tick("write")
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yield fifo.w_en.eq(0)
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yield
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yield
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yield Tick ("write")
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self.assertEqual((yield fifo.w_level), expected_level)
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yield write_done.eq(1)
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@ -355,14 +354,14 @@ class AsyncFIFOSimCase(FHDLTestCase):
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if read:
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yield fifo.r_en.eq(1)
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while not (yield write_done):
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yield
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yield Tick("read")
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self.assertEqual((yield fifo.r_level), expected_level)
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simulator = Simulator(fifo)
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simulator.add_clock(100e-6, domain="write")
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simulator.add_sync_process(write_process, domain="write")
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simulator.add_testbench(write_process)
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simulator.add_clock(50e-6, domain="read")
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simulator.add_sync_process(read_process, domain="read")
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simulator.add_testbench(read_process)
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with simulator.write_vcd("test.vcd"):
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simulator.run()
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@ -435,29 +435,30 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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def test_counter_process(self):
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self.setUp_counter()
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with _ignore_deprecated():
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with self.assertSimulation(self.m) as sim:
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def process():
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self.assertEqual((yield self.count), 4)
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with self.assertSimulation(self.m) as sim:
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def process():
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self.assertEqual((yield self.count), 4)
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yield Delay(1e-6)
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self.assertEqual((yield self.count), 4)
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yield self.sync.clk.eq(1)
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self.assertEqual((yield self.count), 4)
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with _ignore_deprecated():
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yield Settle()
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self.assertEqual((yield self.count), 5)
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yield Delay(1e-6)
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self.assertEqual((yield self.count), 5)
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yield self.sync.clk.eq(0)
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self.assertEqual((yield self.count), 5)
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with _ignore_deprecated():
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yield Settle()
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self.assertEqual((yield self.count), 5)
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for _ in range(3):
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yield Delay(1e-6)
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self.assertEqual((yield self.count), 4)
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yield self.sync.clk.eq(1)
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self.assertEqual((yield self.count), 4)
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yield Settle()
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self.assertEqual((yield self.count), 5)
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yield Delay(1e-6)
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self.assertEqual((yield self.count), 5)
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yield self.sync.clk.eq(0)
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self.assertEqual((yield self.count), 5)
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yield Settle()
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self.assertEqual((yield self.count), 5)
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for _ in range(3):
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yield Delay(1e-6)
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yield self.sync.clk.eq(1)
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yield Delay(1e-6)
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yield self.sync.clk.eq(0)
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self.assertEqual((yield self.count), 0)
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sim.add_process(process)
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self.assertEqual((yield self.count), 0)
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sim.add_process(process)
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def test_counter_clock_and_sync_process(self):
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self.setUp_counter()
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@ -472,7 +473,8 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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for _ in range(3):
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yield
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self.assertEqual((yield self.count), 0)
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sim.add_sync_process(process)
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with _ignore_deprecated():
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sim.add_sync_process(process)
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def test_reset(self):
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self.setUp_counter()
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@ -481,14 +483,15 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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times = 0
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def process():
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nonlocal times
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yield Tick()
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self.assertEqual((yield self.count), 4)
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yield
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yield Tick()
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self.assertEqual((yield self.count), 5)
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yield
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yield Tick()
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self.assertEqual((yield self.count), 6)
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yield
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yield Tick()
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times += 1
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sim.add_sync_process(process)
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sim.add_process(process)
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sim.run()
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sim.reset()
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sim.run()
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@ -520,19 +523,37 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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def process():
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yield self.a.eq(5)
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yield self.b.eq(1)
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yield
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yield Tick()
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self.assertEqual((yield self.x), 4)
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yield
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yield Tick()
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self.assertEqual((yield self.o), 6)
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yield self.s.eq(1)
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yield
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yield
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yield Tick()
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yield Tick()
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self.assertEqual((yield self.o), 4)
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yield self.s.eq(2)
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yield
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yield
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yield Tick()
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yield Tick()
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self.assertEqual((yield self.o), 0)
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sim.add_sync_process(process)
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sim.add_process(process)
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def test_alu_bench(self):
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self.setUp_alu()
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with self.assertSimulation(self.m) as sim:
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sim.add_clock(1e-6)
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def process():
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yield self.a.eq(5)
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yield self.b.eq(1)
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self.assertEqual((yield self.x), 4)
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yield Tick()
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self.assertEqual((yield self.o), 6)
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yield self.s.eq(1)
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yield Tick()
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self.assertEqual((yield self.o), 4)
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yield self.s.eq(2)
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yield Tick()
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self.assertEqual((yield self.o), 0)
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sim.add_testbench(process)
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def setUp_clock_phase(self):
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self.m = Module()
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@ -543,10 +564,10 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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self.check = self.m.domains.check = ClockDomain()
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self.expected = [
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[0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0],
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[0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1],
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[0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1],
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0],
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[0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0],
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[0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1],
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[0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1],
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0],
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]
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def test_clock_phase(self):
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@ -567,11 +588,11 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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self.phase270.clk
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]
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for i in range(16):
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yield
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yield Tick("check")
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for j, c in enumerate(clocks):
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self.assertEqual((yield c), self.expected[j][i])
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sim.add_sync_process(proc, domain="check")
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sim.add_process(proc)
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def setUp_multiclock(self):
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self.sys = ClockDomain()
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@ -588,15 +609,15 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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def sys_process():
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yield Passive()
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yield
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yield
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yield Tick("sys")
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yield Tick("sys")
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self.fail()
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def pix_process():
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yield
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yield
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yield
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sim.add_sync_process(sys_process, domain="sys")
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sim.add_sync_process(pix_process, domain="pix")
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yield Tick("pix")
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yield Tick("pix")
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yield Tick("pix")
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sim.add_testbench(sys_process)
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sim.add_testbench(pix_process)
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def setUp_lhs_rhs(self):
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self.i = Signal(8)
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@ -644,7 +665,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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with self.assertSimulation(Module()) as sim:
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with self.assertRaisesRegex(TypeError,
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r"^Cannot add a process 1 because it is not a generator function$"):
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sim.add_sync_process(1)
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sim.add_process(1)
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def test_add_process_wrong_generator(self):
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with self.assertSimulation(Module()) as sim:
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@ -652,7 +673,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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r"^Cannot add a process <.+?> because it is not a generator function$"):
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def process():
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yield Delay()
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sim.add_sync_process(process())
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sim.add_process(process())
|
||||
|
||||
def test_add_clock_wrong_twice(self):
|
||||
m = Module()
|
||||
|
|
@ -678,31 +699,14 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
|
||||
def test_command_wrong(self):
|
||||
survived = False
|
||||
with _ignore_deprecated():
|
||||
with self.assertSimulation(Module()) as sim:
|
||||
def process():
|
||||
nonlocal survived
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"Received unsupported command 1 from process .+?"):
|
||||
yield 1
|
||||
survived = True
|
||||
sim.add_process(process)
|
||||
self.assertTrue(survived)
|
||||
|
||||
def test_sync_command_deprecated(self):
|
||||
survived = False
|
||||
m = Module()
|
||||
dummy = Signal()
|
||||
m.d.sync += dummy.eq(1)
|
||||
with self.assertSimulation(m) as sim:
|
||||
with self.assertSimulation(Module()) as sim:
|
||||
def process():
|
||||
nonlocal survived
|
||||
with self.assertWarnsRegex(DeprecationWarning,
|
||||
r"Using `Delay` is deprecated within `add_sync_process`"):
|
||||
yield Delay(1e-8)
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"Received unsupported command 1 from process .+?"):
|
||||
yield 1
|
||||
survived = True
|
||||
sim.add_sync_process(process)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_process(process)
|
||||
self.assertTrue(survived)
|
||||
|
||||
def test_sync_command_wrong(self):
|
||||
|
|
@ -717,7 +721,8 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
r"Received unsupported command 1 from process .+?"):
|
||||
yield 1
|
||||
survived = True
|
||||
sim.add_sync_process(process)
|
||||
with _ignore_deprecated():
|
||||
sim.add_sync_process(process)
|
||||
sim.add_clock(1e-6)
|
||||
self.assertTrue(survived)
|
||||
|
||||
|
|
@ -762,15 +767,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
with self.assertSimulation(self.m) as sim:
|
||||
def process():
|
||||
yield self.rdport.addr.eq(1)
|
||||
yield
|
||||
yield
|
||||
yield Tick()
|
||||
self.assertEqual((yield self.rdport.data), 0x55)
|
||||
yield self.rdport.addr.eq(2)
|
||||
yield
|
||||
yield
|
||||
yield Tick()
|
||||
self.assertEqual((yield self.rdport.data), 0x00)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_memory_write(self):
|
||||
self.setUp_memory()
|
||||
|
|
@ -779,13 +782,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
yield self.wrport.addr.eq(4)
|
||||
yield self.wrport.data.eq(0x33)
|
||||
yield self.wrport.en.eq(1)
|
||||
yield
|
||||
yield Tick()
|
||||
yield self.wrport.en.eq(0)
|
||||
yield self.rdport.addr.eq(4)
|
||||
yield
|
||||
yield Tick()
|
||||
self.assertEqual((yield self.rdport.data), 0x33)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_memory_write_granularity(self):
|
||||
self.setUp_memory(wr_granularity=4)
|
||||
|
|
@ -864,14 +867,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
self.m.submodules.rdport = self.rdport = self.memory.read_port()
|
||||
with self.assertSimulation(self.m) as sim:
|
||||
def process():
|
||||
yield
|
||||
yield Tick()
|
||||
self.assertEqual((yield self.rdport.data), 0xaa)
|
||||
yield self.rdport.addr.eq(1)
|
||||
yield
|
||||
yield
|
||||
yield Tick()
|
||||
self.assertEqual((yield self.rdport.data), 0x55)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_comb_bench_process(self):
|
||||
m = Module()
|
||||
|
|
@ -1022,11 +1024,11 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
self.assertEqual((yield self.memory[Const(2)]), 0x00)
|
||||
yield self.memory[Const(1)].eq(Const(0x33))
|
||||
self.assertEqual((yield self.memory[Const(1)]), 0x55)
|
||||
yield
|
||||
yield Tick()
|
||||
self.assertEqual((yield self.memory[Const(1)]), 0x33)
|
||||
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process)
|
||||
sim.add_process(process)
|
||||
|
||||
def test_vcd_wrong_nonzero_time(self):
|
||||
s = Signal()
|
||||
|
|
|
|||
Loading…
Reference in a new issue