hdl.dsl: check for unique domain name.

Fixes #385.
This commit is contained in:
whitequark 2020-05-19 23:40:49 +00:00
parent fbf9e1f339
commit 404b2e07e4
2 changed files with 15 additions and 6 deletions

View file

@ -712,7 +712,7 @@ class DSLTestCase(FHDLTestCase):
m = Module()
m.domains.foo = ClockDomain()
self.assertEqual(len(m._domains), 1)
self.assertEqual(m._domains[0].name, "foo")
self.assertEqual(m._domains["foo"].name, "foo")
def test_domain_add_wrong(self):
m = Module()
@ -729,6 +729,13 @@ class DSLTestCase(FHDLTestCase):
msg="Clock domain name 'bar' must match name in `m.domains.foo += ...` syntax"):
m.domains.foo = ClockDomain("bar")
def test_domain_add_wrong_duplicate(self):
m = Module()
m.domains += ClockDomain("foo")
with self.assertRaises(NameError,
msg="Clock domain named 'foo' already exists"):
m.domains += ClockDomain("foo")
def test_lower(self):
m1 = Module()
m1.d.comb += self.c1.eq(self.s1)