parent
fbf9e1f339
commit
404b2e07e4
2 changed files with 15 additions and 6 deletions
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@ -712,7 +712,7 @@ class DSLTestCase(FHDLTestCase):
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m = Module()
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m.domains.foo = ClockDomain()
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self.assertEqual(len(m._domains), 1)
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self.assertEqual(m._domains[0].name, "foo")
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self.assertEqual(m._domains["foo"].name, "foo")
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def test_domain_add_wrong(self):
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m = Module()
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@ -729,6 +729,13 @@ class DSLTestCase(FHDLTestCase):
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msg="Clock domain name 'bar' must match name in `m.domains.foo += ...` syntax"):
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m.domains.foo = ClockDomain("bar")
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def test_domain_add_wrong_duplicate(self):
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m = Module()
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m.domains += ClockDomain("foo")
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with self.assertRaises(NameError,
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msg="Clock domain named 'foo' already exists"):
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m.domains += ClockDomain("foo")
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def test_lower(self):
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m1 = Module()
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m1.d.comb += self.c1.eq(self.s1)
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