vendor.xilinx_spartan6: implement DDR I/O buffers and inverters.
This commit is contained in:
Jean-François Nguyen
whitequark
parent
2566747061
commit
412781e0c3
236
nmigen/vendor/xilinx_spartan6.py
vendored
236
nmigen/vendor/xilinx_spartan6.py
vendored
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@ -126,150 +126,212 @@ class XilinxSpartan6Platform(TemplatedPlatform):
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"""
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"""
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]
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]
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def _get_dff(self, m, clk, d, q):
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def _get_xdr_buffer(self, m, pin, i_invert=None, o_invert=None):
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# SDR I/O is performed by packing a flip-flop into the pad IOB.
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def get_dff(clk, d, q):
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for bit in range(len(q)):
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# SDR I/O is performed by packing a flip-flop into the pad IOB.
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_q = Signal()
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for bit in range(len(q)):
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_q.attrs["IOB"] = "TRUE"
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_q = Signal()
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m.submodules += Instance("FDCE",
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_q.attrs["IOB"] = "TRUE"
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i_C=clk,
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m.submodules += Instance("FDCE",
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i_CE=Const(1),
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i_C=clk,
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i_CLR=Const(0),
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i_CE=Const(1),
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i_D=d[bit],
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i_CLR=Const(0),
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o_Q=_q,
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i_D=d[bit],
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)
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o_Q=_q,
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m.d.comb += q[bit].eq(_q)
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)
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m.d.comb += q[bit].eq(_q)
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def get_iddr(clk, d, q0, q1):
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for bit in range(len(q0)):
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m.submodules += Instance("IDDR2",
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p_DDR_ALIGNMENT="C0",
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p_SRTYPE="ASYNC",
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p_INIT_Q0=0, p_INIT_Q1=0,
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i_C0=clk, i_C1=~clk,
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i_CE=Const(1),
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i_S=Const(0), i_R=Const(0),
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i_D=d[bit],
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o_Q0=q0[bit], o_Q1=q1[bit]
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)
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def get_oddr(clk, d0, d1, q):
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for bit in range(len(q)):
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m.submodules += Instance("ODDR2",
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p_DDR_ALIGNMENT="C0",
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p_SRTYPE="ASYNC",
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p_INIT=0,
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i_C0=clk, i_C1=~clk,
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i_CE=Const(1),
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i_S=Const(0), i_R=Const(0),
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i_D0=d0[bit], i_D1=d1[bit],
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o_Q=q[bit]
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)
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def get_i_inverter(y, invert):
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if invert is None:
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return y
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else:
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a = Signal.like(y, name_suffix="_x{}".format(1 if invert else 0))
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for bit in range(len(y)):
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m.submodules += Instance("LUT1",
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p_INIT=0b01 if invert else 0b10,
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i_I0=a[bit],
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o_O=y[bit]
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)
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return a
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def get_o_inverter(a, invert):
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if invert is None:
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return a
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else:
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y = Signal.like(a, name_suffix="_x{}".format(1 if invert else 0))
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for bit in range(len(a)):
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m.submodules += Instance("LUT1",
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p_INIT=0b01 if invert else 0b10,
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i_I0=a[bit],
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o_O=y[bit]
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)
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return y
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if "i" in pin.dir:
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if pin.xdr < 2:
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pin_i = get_i_inverter(pin.i, i_invert)
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elif pin.xdr == 2:
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pin_i0 = get_i_inverter(pin.i0, i_invert)
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pin_i1 = get_i_inverter(pin.i1, i_invert)
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = get_o_inverter(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = get_o_inverter(pin.o0, o_invert)
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pin_o1 = get_o_inverter(pin.o1, o_invert)
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i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
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o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
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oe = Signal(1, name="{}_xdr_oe".format(pin.name))
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if pin.xdr == 0:
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if "i" in pin.dir:
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m.d.comb += pin_i.eq(i)
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if "o" in pin.dir:
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m.d.comb += o.eq(pin_o)
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if pin.dir in ("oe", "io"):
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m.d.comb += oe.eq(pin.oe)
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elif pin.xdr == 1:
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if "i" in pin.dir:
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get_dff(pin.i_clk, i, pin_i)
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if "o" in pin.dir:
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get_dff(pin.o_clk, pin_o, o)
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if pin.dir in ("oe", "io"):
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get_dff(pin.o_clk, pin.oe, oe)
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elif pin.xdr == 2:
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if "i" in pin.dir:
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# Re-register first input before it enters fabric. This allows both inputs to
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# enter fabric on the same clock edge, and adds one cycle of latency.
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i0_ff = Signal.like(pin_i0, name_suffix="_ff")
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get_dff(pin.i_clk, i0_ff, pin_i0)
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get_iddr(pin.i_clk, i, i0_ff, pin_i1)
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if "o" in pin.dir:
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get_oddr(pin.o_clk, pin_o0, pin_o1, o)
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if pin.dir in ("oe", "io"):
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get_dff(pin.o_clk, pin.oe, oe)
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else:
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assert False
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return (i, o, oe)
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def get_input(self, pin, port, attrs, invert):
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def get_input(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended input", pin, attrs,
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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m = Module()
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if pin.xdr == 1:
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i, o, oe = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
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self._get_dff(m, pin.i_clk, port, pin.i)
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m.d.comb += i.eq(port)
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else:
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m.d.comb += pin.i.eq(port)
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return m
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return m
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def get_output(self, pin, port, attrs, invert):
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def get_output(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended output", pin, attrs,
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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m = Module()
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if pin.xdr == 1:
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i, o, oe = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
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self._get_dff(m, pin.o_clk, pin.o, port)
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m.d.comb += port.eq(o)
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else:
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m.d.comb += port.eq(pin.o)
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return m
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return m
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def get_tristate(self, pin, port, attrs, invert):
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def get_tristate(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended tristate", pin, attrs,
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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m = Module()
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if pin.xdr == 1:
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i, o, oe = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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for bit in range(len(port)):
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for bit in range(len(port)):
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m.submodules += Instance("OBUFT",
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m.submodules += Instance("OBUFT",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_T=~oe,
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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i_I=o[bit],
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o_O=port[bit]
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o_O=port[bit]
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)
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)
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return m
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return m
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def get_input_output(self, pin, port, attrs, invert):
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def get_input_output(self, pin, port, attrs, invert):
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assert not invert
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self._check_feature("single-ended input/output", pin, attrs,
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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m = Module()
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if pin.xdr == 1:
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i, o, oe = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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o_invert=True if invert else None)
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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i_ff = Signal.like(pin.i, name="{}_ff".format(pin.i.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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self._get_dff(m, pin.i_clk, i_ff, pin.i)
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for bit in range(len(port)):
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for bit in range(len(port)):
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m.submodules += Instance("IOBUF",
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m.submodules += Instance("IOBUF",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_T=~oe,
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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i_I=o[bit],
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o_O=i_ff[bit] if pin.xdr == 1 else pin.i[bit],
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o_O=i[bit],
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io_IO=port[bit]
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io_IO=port[bit]
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)
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)
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return m
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return m
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def get_diff_input(self, pin, p_port, n_port, attrs, invert):
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def get_diff_input(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential input", pin, attrs,
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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m = Module()
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if pin.xdr == 1:
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i, o, oe = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
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i_ff = Signal.like(pin.i, name="{}_ff".format(pin.i.name))
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self._get_dff(m, pin.i_clk, i_ff, pin.i)
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for bit in range(len(p_port)):
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for bit in range(len(p_port)):
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m.submodules += Instance("IBUFDS",
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m.submodules += Instance("IBUFDS",
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i_I=p_port[bit],
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i_I=p_port[bit], i_IB=n_port[bit],
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i_IB=n_port[bit],
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o_O=i[bit]
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o_O=i_ff[bit] if pin.xdr == 1 else pin.i[bit]
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)
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)
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return m
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return m
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def get_diff_output(self, pin, p_port, n_port, attrs, invert):
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def get_diff_output(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential output", pin, attrs,
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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m = Module()
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if pin.xdr == 1:
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i, o, oe = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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for bit in range(len(p_port)):
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for bit in range(len(p_port)):
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m.submodules += Instance("OBUFDS",
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m.submodules += Instance("OBUFDS",
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o_O=p_port[bit],
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i_I=o[bit],
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o_OB=n_port[bit],
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o_O=p_port[bit], o_OB=n_port[bit]
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit]
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)
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)
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return m
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return m
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def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
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def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential tristate", pin, attrs,
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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m = Module()
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if pin.xdr == 1:
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i, o, oe = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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for bit in range(len(p_port)):
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for bit in range(len(p_port)):
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m.submodules += Instance("OBUFTDS",
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m.submodules += Instance("OBUFTDS",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_T=~oe,
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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i_I=o[bit],
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o_O=p_port[bit],
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o_O=p_port[bit], o_OB=n_port[bit]
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o_OB=n_port[bit]
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)
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)
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return m
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return m
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def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
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def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
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assert not invert
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self._check_feature("differential input/output", pin, attrs,
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(0, 1), valid_attrs=True)
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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m = Module()
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if pin.xdr == 1:
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i, o, oe = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
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o_ff = Signal.like(pin.o, name="{}_ff".format(pin.o.name))
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o_invert=True if invert else None)
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oe_ff = Signal.like(pin.oe, name="{}_ff".format(pin.oe.name))
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i_ff = Signal.like(pin.i, name="{}_ff".format(pin.i.name))
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self._get_dff(m, pin.o_clk, pin.o, o_ff)
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self._get_dff(m, pin.o_clk, pin.oe, oe_ff)
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self._get_dff(m, pin.i_clk, i_ff, pin.i)
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for bit in range(len(p_port)):
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for bit in range(len(p_port)):
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m.submodules += Instance("IOBUFDS",
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m.submodules += Instance("IOBUFDS",
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i_T=~(oe_ff if pin.xdr == 1 else pin.oe),
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i_T=~oe,
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i_I=o_ff[bit] if pin.xdr == 1 else pin.o[bit],
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i_I=o[bit],
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o_O=i_ff[bit] if pin.xdr == 1 else pin.i[bit],
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o_O=i[bit],
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io_IO=p_port[bit],
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io_IO=p_port[bit], io_IOB=n_port[bit]
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io_IOB=n_port[bit]
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)
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)
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return m
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return m
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