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vendor.fpga.lattice_ice40: implement differential input buffers.

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This commit is contained in:
whitequark 2019-06-03 08:38:12 +00:00
parent 3116d4add2
commit 41adcc3f97
4 changed files with 43 additions and 17 deletions
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8
nmigen/build/plat.py
View file

@ -134,13 +134,13 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
for pin, p_port, n_port, extras in self.iter_differential_pins():
if pin.dir == "i":
add_pin_fragment(pin, self.get_diff_input(pin, p_port, n_port))
add_pin_fragment(pin, self.get_diff_input(pin, p_port, n_port, extras))
if pin.dir == "o":
add_pin_fragment(pin, self.get_diff_output(pin, p_port, n_port))
add_pin_fragment(pin, self.get_diff_output(pin, p_port, n_port, extras))
if pin.dir == "oe":
add_pin_fragment(pin, self.get_diff_tristate(pin, p_port, n_port))
add_pin_fragment(pin, self.get_diff_tristate(pin, p_port, n_port, extras))
if pin.dir == "io":
add_pin_fragment(pin, self.get_diff_input_output(pin, p_port, n_port))
add_pin_fragment(pin, self.get_diff_input_output(pin, p_port, n_port, extras))
return self.toolchain_prepare(fragment, name, **kwargs)

10
nmigen/build/res.py
View file

@ -156,17 +156,13 @@ class ConstraintManager:
else:
assert False
def iter_port_constraints(self, diff_pins="pn"):
def iter_port_constraints(self):
for resource, pin, port in self._ports:
if isinstance(resource.io[0], Pins):
yield port.io.name, resource.io[0].names, resource.extras
elif isinstance(resource.io[0], DiffPairs):
# On some FPGAs like iCE40, only one pin out of two in a differential pair may be
# constrained. The other has to be completely disconnected.
if "p" in diff_pins:
yield port.p.name, resource.io[0].p.names, resource.extras
if "n" in diff_pins:
yield port.n.name, resource.io[0].n.names, resource.extras
yield port.p.name, resource.io[0].p.names, resource.extras
yield port.n.name, resource.io[0].n.names, resource.extras
else:
assert False