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sim._pyrtl: mask Mux selection operand.

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Otherwise it behaves funny when it's eg. the result of operator ~.
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Marcelina Kościelnicka 2020-11-14 16:22:34 +01:00 committed by GitHub
parent adef3b2e7b
commit 44318149e0
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2 changed files with 6 additions and 1 deletions
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2
nmigen/sim/_pyrtl.py
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@ -177,7 +177,7 @@ class _RHSValueCompiler(_ValueCompiler):
elif len(value.operands) == 3:
if value.operator == "m":
sel, val1, val0 = value.operands
return f"({self(val1)} if {self(sel)} else {self(val0)})"
return f"({self(val1)} if {mask(sel)} else {self(val0)})"
raise NotImplementedError("Operator '{}' not implemented".format(value.operator)) # :nocov:
def on_Slice(self, value):

5
tests/test_sim.py
View file

@ -186,6 +186,11 @@ class SimulatorUnitTestCase(FHDLTestCase):
self.assertStatement(stmt, [C(2, 4), C(3, 4), C(0)], C(3, 4))
self.assertStatement(stmt, [C(2, 4), C(3, 4), C(1)], C(2, 4))
def test_mux_invert(self):
stmt = lambda y, a, b, c: y.eq(Mux(~c, a, b))
self.assertStatement(stmt, [C(2, 4), C(3, 4), C(0)], C(2, 4))
self.assertStatement(stmt, [C(2, 4), C(3, 4), C(1)], C(3, 4))
def test_abs(self):
stmt = lambda y, a: y.eq(abs(a))
self.assertStatement(stmt, [C(3, unsigned(8))], C(3, unsigned(8)))