hdl.dsl: add a diagnostic for m.d.submodules += ....

This commit is contained in:
whitequark 2019-09-28 17:50:24 +00:00
parent a02e3750bf
commit 450d7efdf2
2 changed files with 17 additions and 5 deletions

View file

@ -96,6 +96,13 @@ class DSLTestCase(FHDLTestCase):
msg="'Module' object has no attribute 'nonexistentattr'"):
m.nonexistentattr
def test_d_suspicious(self):
m = Module()
with self.assertWarns(SyntaxWarning,
msg="Using '<module>.d.submodules' would add statements to clock domain "
"'submodules'; did you mean <module>.submodules instead?"):
m.d.submodules += []
def test_clock_signal(self):
m = Module()
m.d.comb += ClockSignal("pix").eq(ClockSignal())