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hdl.dsl: add a diagnostic for m.d.submodules += ....

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This commit is contained in:
whitequark 2019-09-28 17:50:24 +00:00
parent a02e3750bf
commit 450d7efdf2
2 changed files with 17 additions and 5 deletions
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15
nmigen/hdl/dsl.py
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@ -28,7 +28,7 @@ class _ModuleBuilderProxy:
object.__setattr__(self, "_depth", depth) object.__setattr__(self, "_depth", depth)
class _ModuleBuilderDomainExplicit(_ModuleBuilderProxy): class _ModuleBuilderDomain(_ModuleBuilderProxy):
def __init__(self, builder, depth, domain): def __init__(self, builder, depth, domain):
super().__init__(builder, depth) super().__init__(builder, depth)
self._domain = domain self._domain = domain
@ -38,13 +38,18 @@ class _ModuleBuilderDomainExplicit(_ModuleBuilderProxy):
return self return self
class _ModuleBuilderDomainImplicit(_ModuleBuilderProxy): class _ModuleBuilderDomains(_ModuleBuilderProxy):
def __getattr__(self, name): def __getattr__(self, name):
if name == "submodules":
warnings.warn("Using '<module>.d.{}' would add statements to clock domain {!r}; "
"did you mean <module>.{} instead?"
.format(name, name, name),
SyntaxWarning, stacklevel=2)
if name == "comb": if name == "comb":
domain = None domain = None
else: else:
domain = name domain = name
return _ModuleBuilderDomainExplicit(self._builder, self._depth, domain) return _ModuleBuilderDomain(self._builder, self._depth, domain)
def __getitem__(self, name): def __getitem__(self, name):
return self.__getattr__(name) return self.__getattr__(name)
@ -52,7 +57,7 @@ class _ModuleBuilderDomainImplicit(_ModuleBuilderProxy):
def __setattr__(self, name, value): def __setattr__(self, name, value):
if name == "_depth": if name == "_depth":
object.__setattr__(self, name, value) object.__setattr__(self, name, value)
elif not isinstance(value, _ModuleBuilderDomainExplicit): elif not isinstance(value, _ModuleBuilderDomain):
raise AttributeError("Cannot assign 'd.{}' attribute; did you mean 'd.{} +='?" raise AttributeError("Cannot assign 'd.{}' attribute; did you mean 'd.{} +='?"
.format(name, name)) .format(name, name))
@ -63,7 +68,7 @@ class _ModuleBuilderDomainImplicit(_ModuleBuilderProxy):
class _ModuleBuilderRoot: class _ModuleBuilderRoot:
def __init__(self, builder, depth): def __init__(self, builder, depth):
self._builder = builder self._builder = builder
self.domain = self.d = _ModuleBuilderDomainImplicit(builder, depth) self.domain = self.d = _ModuleBuilderDomains(builder, depth)
def __getattr__(self, name): def __getattr__(self, name):
if name in ("comb", "sync"): if name in ("comb", "sync"):

7
nmigen/test/test_hdl_dsl.py
View file

@ -96,6 +96,13 @@ class DSLTestCase(FHDLTestCase):
msg="'Module' object has no attribute 'nonexistentattr'"): msg="'Module' object has no attribute 'nonexistentattr'"):
m.nonexistentattr m.nonexistentattr
def test_d_suspicious(self):
m = Module()
with self.assertWarns(SyntaxWarning,
msg="Using '<module>.d.submodules' would add statements to clock domain "
"'submodules'; did you mean <module>.submodules instead?"):
m.d.submodules += []
def test_clock_signal(self): def test_clock_signal(self):
m = Module() m = Module()
m.d.comb += ClockSignal("pix").eq(ClockSignal()) m.d.comb += ClockSignal("pix").eq(ClockSignal())