lib.io: Implement *Buffer from RFC 55.
This commit is contained in:
Wanda
Catherine
parent
81eae1dd35
commit
456dcaeb7b
3 changed files with 965 additions and 25 deletions
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@ -1,7 +1,11 @@
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# amaranth: UnusedElaboratable=no
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from amaranth.hdl import *
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from amaranth.sim import *
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from amaranth.hdl._ir import build_netlist
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from amaranth.lib.io import *
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from amaranth.lib.wiring import *
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from amaranth.lib import wiring, data
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from .utils import *
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@ -169,6 +173,548 @@ class DifferentialPortTestCase(FHDLTestCase):
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self.assertRepr(iport, "DifferentialPort((io-port iop), (io-port ion), invert=(False, True, False, True), direction=Direction.Output)")
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class BufferTestCase(FHDLTestCase):
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def test_signature(self):
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sig_i = Buffer.Signature("i", 4)
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self.assertEqual(sig_i.direction, Direction.Input)
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self.assertEqual(sig_i.width, 4)
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self.assertEqual(sig_i.members, wiring.SignatureMembers({
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"i": wiring.In(4),
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}))
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sig_o = Buffer.Signature("o", 4)
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self.assertEqual(sig_o.direction, Direction.Output)
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self.assertEqual(sig_o.width, 4)
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self.assertEqual(sig_o.members, wiring.SignatureMembers({
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"o": wiring.Out(4),
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"oe": wiring.Out(1, init=1),
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}))
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sig_io = Buffer.Signature("io", 4)
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self.assertEqual(sig_io.direction, Direction.Bidir)
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self.assertEqual(sig_io.width, 4)
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self.assertEqual(sig_io.members, wiring.SignatureMembers({
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"i": wiring.In(4),
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"o": wiring.Out(4),
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"oe": wiring.Out(1, init=0),
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}))
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self.assertNotEqual(sig_i, sig_io)
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self.assertEqual(sig_i, sig_i)
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self.assertRepr(sig_io, "Buffer.Signature(Direction.Bidir, 4)")
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def test_construct(self):
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io = IOPort(4)
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port = SingleEndedPort(io)
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buf = Buffer("i", port)
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self.assertEqual(buf.direction, Direction.Input)
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self.assertIs(buf.port, port)
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self.assertRepr(buf.signature, "Buffer.Signature(Direction.Input, 4).flip()")
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def test_construct_wrong(self):
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io = IOPort(4)
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port_i = SingleEndedPort(io, direction="i")
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port_o = SingleEndedPort(io, direction="o")
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with self.assertRaisesRegex(TypeError,
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r"^'port' must be a 'PortLike', not \(io-port io\)$"):
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Buffer("io", io)
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with self.assertRaisesRegex(ValueError,
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r"^Input port cannot be used with Bidir buffer$"):
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Buffer("io", port_i)
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with self.assertRaisesRegex(ValueError,
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r"^Output port cannot be used with Input buffer$"):
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Buffer("i", port_o)
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def test_elaborate(self):
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io = IOPort(4)
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port = SingleEndedPort(io)
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buf = Buffer("io", port)
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nl = build_netlist(Fragment.get(buf, None), [buf.i, buf.o, buf.oe])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 'o' 0.2:6)
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(input 'oe' 0.6)
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(output 'i' 1.0:4)
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(io inout 'io' 0.0:4)
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)
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(cell 0 0 (top
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(input 'o' 2:6)
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(input 'oe' 6:7)
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(output 'i' 1.0:4)
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))
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(cell 1 0 (iob inout 0.0:4 0.2:6 0.6))
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)
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""")
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port = SingleEndedPort(io, invert=[False, True, False, True])
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buf = Buffer("io", port)
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nl = build_netlist(Fragment.get(buf, None), [buf.i, buf.o, buf.oe])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 'o' 0.2:6)
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(input 'oe' 0.6)
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(output 'i' 2.0:4)
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(io inout 'io' 0.0:4)
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)
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(cell 0 0 (top
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(input 'o' 2:6)
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(input 'oe' 6:7)
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(output 'i' 2.0:4)
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))
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(cell 1 0 (^ 0.2:6 4'd10))
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(cell 2 0 (^ 3.0:4 4'd10))
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(cell 3 0 (iob inout 0.0:4 1.0:4 0.6))
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)
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""")
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buf = Buffer("i", port)
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nl = build_netlist(Fragment.get(buf, None), [buf.i])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(output 'i' 1.0:4)
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(io input 'io' 0.0:4)
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)
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(cell 0 0 (top
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(output 'i' 1.0:4)
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))
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(cell 1 0 (^ 2.0:4 4'd10))
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(cell 2 0 (iob input 0.0:4))
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)
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""")
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buf = Buffer("o", port)
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nl = build_netlist(Fragment.get(buf, None), [buf.o, buf.oe])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 'o' 0.2:6)
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(input 'oe' 0.6)
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(io output 'io' 0.0:4)
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)
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(cell 0 0 (top
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(input 'o' 2:6)
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(input 'oe' 6:7)
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))
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(cell 1 0 (^ 0.2:6 4'd10))
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(cell 2 0 (iob output 0.0:4 1.0:4 0.6))
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)
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""")
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def test_elaborate_diff(self):
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iop = IOPort(4)
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ion = IOPort(4)
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port = DifferentialPort(iop, ion)
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buf = Buffer("io", port)
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nl = build_netlist(Fragment.get(buf, None), [buf.i, buf.o, buf.oe])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 'o' 0.2:6)
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(input 'oe' 0.6)
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(output 'i' 1.0:4)
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(io inout 'iop' 0.0:4)
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(io output 'ion' 1.0:4)
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)
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(cell 0 0 (top
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(input 'o' 2:6)
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(input 'oe' 6:7)
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(output 'i' 1.0:4)
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))
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(cell 1 0 (iob inout 0.0:4 0.2:6 0.6))
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(cell 2 0 (~ 0.2:6))
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(cell 3 0 (iob output 1.0:4 2.0:4 0.6))
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)
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""")
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port = DifferentialPort(iop, ion, invert=[False, True, False, True])
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buf = Buffer("io", port)
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nl = build_netlist(Fragment.get(buf, None), [buf.i, buf.o, buf.oe])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 'o' 0.2:6)
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(input 'oe' 0.6)
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(output 'i' 2.0:4)
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(io inout 'iop' 0.0:4)
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(io output 'ion' 1.0:4)
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)
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(cell 0 0 (top
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(input 'o' 2:6)
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(input 'oe' 6:7)
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(output 'i' 2.0:4)
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))
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(cell 1 0 (^ 0.2:6 4'd10))
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(cell 2 0 (^ 3.0:4 4'd10))
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(cell 3 0 (iob inout 0.0:4 1.0:4 0.6))
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(cell 4 0 (~ 1.0:4))
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(cell 5 0 (iob output 1.0:4 4.0:4 0.6))
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)
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""")
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buf = Buffer("i", port)
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nl = build_netlist(Fragment.get(buf, None), [buf.i])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(output 'i' 1.0:4)
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(io input 'iop' 0.0:4)
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)
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(cell 0 0 (top
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(output 'i' 1.0:4)
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))
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(cell 1 0 (^ 2.0:4 4'd10))
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(cell 2 0 (iob input 0.0:4))
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)
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""")
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buf = Buffer("o", port)
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nl = build_netlist(Fragment.get(buf, None), [buf.o, buf.oe])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 'o' 0.2:6)
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(input 'oe' 0.6)
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(io output 'iop' 0.0:4)
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(io output 'ion' 1.0:4)
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)
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(cell 0 0 (top
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(input 'o' 2:6)
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(input 'oe' 6:7)
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))
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(cell 1 0 (^ 0.2:6 4'd10))
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(cell 2 0 (iob output 0.0:4 1.0:4 0.6))
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(cell 3 0 (~ 1.0:4))
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(cell 4 0 (iob output 1.0:4 3.0:4 0.6))
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)
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""")
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class FFBufferTestCase(FHDLTestCase):
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def test_signature(self):
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sig_i = FFBuffer.Signature("i", 4)
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self.assertEqual(sig_i.direction, Direction.Input)
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self.assertEqual(sig_i.width, 4)
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self.assertEqual(sig_i.members, wiring.SignatureMembers({
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"i": wiring.In(4),
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}))
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sig_o = FFBuffer.Signature("o", 4)
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self.assertEqual(sig_o.direction, Direction.Output)
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self.assertEqual(sig_o.width, 4)
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self.assertEqual(sig_o.members, wiring.SignatureMembers({
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"o": wiring.Out(4),
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"oe": wiring.Out(1, init=1),
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}))
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sig_io = FFBuffer.Signature("io", 4)
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self.assertEqual(sig_io.direction, Direction.Bidir)
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self.assertEqual(sig_io.width, 4)
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self.assertEqual(sig_io.members, wiring.SignatureMembers({
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"i": wiring.In(4),
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"o": wiring.Out(4),
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"oe": wiring.Out(1, init=0),
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}))
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self.assertNotEqual(sig_i, sig_io)
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self.assertEqual(sig_i, sig_i)
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self.assertRepr(sig_io, "FFBuffer.Signature(Direction.Bidir, 4)")
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def test_construct(self):
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io = IOPort(4)
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port = SingleEndedPort(io)
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buf = FFBuffer("i", port)
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self.assertEqual(buf.direction, Direction.Input)
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self.assertIs(buf.port, port)
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self.assertRepr(buf.signature, "FFBuffer.Signature(Direction.Input, 4).flip()")
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self.assertEqual(buf.i_domain, "sync")
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with self.assertRaisesRegex(AttributeError,
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r"^Input buffer doesn't have an output domain$"):
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buf.o_domain
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buf = FFBuffer("i", port, i_domain="inp")
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self.assertEqual(buf.i_domain, "inp")
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buf = FFBuffer("o", port)
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self.assertEqual(buf.direction, Direction.Output)
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self.assertIs(buf.port, port)
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self.assertRepr(buf.signature, "FFBuffer.Signature(Direction.Output, 4).flip()")
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self.assertEqual(buf.o_domain, "sync")
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with self.assertRaisesRegex(AttributeError,
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r"^Output buffer doesn't have an input domain$"):
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buf.i_domain
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buf = FFBuffer("o", port, o_domain="out")
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self.assertEqual(buf.o_domain, "out")
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buf = FFBuffer("io", port)
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self.assertEqual(buf.direction, Direction.Bidir)
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self.assertIs(buf.port, port)
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self.assertRepr(buf.signature, "FFBuffer.Signature(Direction.Bidir, 4).flip()")
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self.assertEqual(buf.i_domain, "sync")
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self.assertEqual(buf.o_domain, "sync")
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buf = FFBuffer("io", port, i_domain="input", o_domain="output")
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self.assertEqual(buf.i_domain, "input")
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self.assertEqual(buf.o_domain, "output")
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def test_construct_wrong(self):
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io = IOPort(4)
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port = SingleEndedPort(io)
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port_i = SingleEndedPort(io, direction="i")
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port_o = SingleEndedPort(io, direction="o")
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with self.assertRaisesRegex(TypeError,
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r"^'port' must be a 'PortLike', not \(io-port io\)$"):
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FFBuffer("io", io)
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with self.assertRaisesRegex(ValueError,
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r"^Input port cannot be used with Bidir buffer$"):
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FFBuffer("io", port_i)
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with self.assertRaisesRegex(ValueError,
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r"^Output port cannot be used with Input buffer$"):
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FFBuffer("i", port_o)
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with self.assertRaisesRegex(ValueError,
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r"^Input buffer doesn't have an output domain$"):
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FFBuffer("i", port, o_domain="output")
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with self.assertRaisesRegex(ValueError,
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r"^Output buffer doesn't have an input domain$"):
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FFBuffer("o", port, i_domain="input")
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def test_elaborate(self):
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io = IOPort(4)
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port = SingleEndedPort(io)
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m = Module()
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m.domains.inp = ClockDomain()
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m.domains.outp = ClockDomain()
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m.submodules.buf = buf = FFBuffer("io", port, i_domain="inp", o_domain="outp")
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nl = build_netlist(Fragment.get(m, None), [
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buf.i, buf.o, buf.oe,
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ClockSignal("inp"), ResetSignal("inp"),
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ClockSignal("outp"), ResetSignal("outp"),
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])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 'o' 0.2:6)
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(input 'oe' 0.6)
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(input 'inp_clk' 0.7)
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(input 'inp_rst' 0.8)
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(input 'outp_clk' 0.9)
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(input 'outp_rst' 0.10)
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(output 'i' 2.0:4)
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(io inout 'io' 0.0:4)
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)
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(module 1 0 ('top' 'buf')
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(input 'o$11' 0.2:6)
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(input 'oe$12' 0.6)
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(input 'inp_clk' 0.7)
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(input 'inp_rst' 0.8)
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(input 'outp_clk' 0.9)
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(input 'outp_rst' 0.10)
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(output 'i_ff' 2.0:4)
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(io inout 'io' 0.0:4)
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)
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(module 2 1 ('top' 'buf' 'io_buffer')
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(output 'i' 1.0:4)
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(input 'o' 3.0:4)
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(input 'oe' 4.0)
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(io inout 'io' 0.0:4)
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)
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(cell 0 0 (top
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(input 'o' 2:6)
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(input 'oe' 6:7)
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(input 'inp_clk' 7:8)
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(input 'inp_rst' 8:9)
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(input 'outp_clk' 9:10)
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(input 'outp_rst' 10:11)
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(output 'i' 2.0:4)
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))
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(cell 1 2 (iob inout 0.0:4 3.0:4 4.0))
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(cell 2 1 (flipflop 1.0:4 0 pos 0.7 0))
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(cell 3 1 (flipflop 0.2:6 0 pos 0.9 0))
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(cell 4 1 (flipflop 0.6 0 pos 0.9 0))
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)
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""")
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port = SingleEndedPort(io, invert=[False, True, False, True])
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m = Module()
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m.domains.inp = ClockDomain(reset_less=True)
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m.domains.outp = ClockDomain(reset_less=True)
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m.submodules.buf = buf = FFBuffer("io", port, i_domain="inp", o_domain="outp")
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nl = build_netlist(Fragment.get(m, None), [
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buf.i, buf.o, buf.oe,
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ClockSignal("inp"), ClockSignal("outp"),
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])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 'o' 0.2:6)
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(input 'oe' 0.6)
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(input 'inp_clk' 0.7)
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(input 'outp_clk' 0.8)
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(output 'i' 4.0:4)
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(io inout 'io' 0.0:4)
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)
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(module 1 0 ('top' 'buf')
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(input 'o$9' 0.2:6)
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(input 'oe$10' 0.6)
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(input 'inp_clk' 0.7)
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(input 'outp_clk' 0.8)
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(output 'i_ff' 4.0:4)
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(io inout 'io' 0.0:4)
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)
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(module 2 1 ('top' 'buf' 'io_buffer')
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(output 'i' 2.0:4)
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(input 'o' 5.0:4)
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(input 'oe' 6.0)
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(io inout 'io' 0.0:4)
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)
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(cell 0 0 (top
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(input 'o' 2:6)
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(input 'oe' 6:7)
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(input 'inp_clk' 7:8)
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(input 'outp_clk' 8:9)
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(output 'i' 4.0:4)
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))
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(cell 1 2 (^ 5.0:4 4'd10))
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(cell 2 2 (^ 3.0:4 4'd10))
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(cell 3 2 (iob inout 0.0:4 1.0:4 6.0))
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(cell 4 1 (flipflop 2.0:4 0 pos 0.7 0))
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(cell 5 1 (flipflop 0.2:6 0 pos 0.8 0))
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(cell 6 1 (flipflop 0.6 0 pos 0.8 0))
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)
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""")
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buf = FFBuffer("i", port)
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nl = build_netlist(Fragment.get(buf, None), [buf.i])
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self.assertRepr(nl, """
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(
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(module 0 None ('top')
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(input 'clk' 0.2)
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(input 'rst' 0.3)
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(output 'i' 3.0:4)
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||||
(io input 'io' 0.0:4)
|
||||
)
|
||||
(module 1 0 ('top' 'io_buffer')
|
||||
(output 'i' 1.0:4)
|
||||
(io input 'io' 0.0:4)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(input 'clk' 2:3)
|
||||
(input 'rst' 3:4)
|
||||
(output 'i' 3.0:4)
|
||||
))
|
||||
(cell 1 1 (^ 2.0:4 4'd10))
|
||||
(cell 2 1 (iob input 0.0:4))
|
||||
(cell 3 0 (flipflop 1.0:4 0 pos 0.2 0))
|
||||
)
|
||||
""")
|
||||
|
||||
buf = FFBuffer("o", port)
|
||||
nl = build_netlist(Fragment.get(buf, None), [buf.o, buf.oe])
|
||||
self.assertRepr(nl, """
|
||||
(
|
||||
(module 0 None ('top')
|
||||
(input 'o' 0.2:6)
|
||||
(input 'oe' 0.6)
|
||||
(input 'clk' 0.7)
|
||||
(input 'rst' 0.8)
|
||||
(io output 'io' 0.0:4)
|
||||
)
|
||||
(module 1 0 ('top' 'io_buffer')
|
||||
(input 'o' 3.0:4)
|
||||
(input 'oe' 4.0)
|
||||
(io output 'io' 0.0:4)
|
||||
)
|
||||
(cell 0 0 (top
|
||||
(input 'o' 2:6)
|
||||
(input 'oe' 6:7)
|
||||
(input 'clk' 7:8)
|
||||
(input 'rst' 8:9)
|
||||
))
|
||||
(cell 1 1 (^ 3.0:4 4'd10))
|
||||
(cell 2 1 (iob output 0.0:4 1.0:4 4.0))
|
||||
(cell 3 0 (flipflop 0.2:6 0 pos 0.7 0))
|
||||
(cell 4 0 (flipflop 0.6 0 pos 0.7 0))
|
||||
)
|
||||
""")
|
||||
|
||||
|
||||
class DDRBufferTestCase(FHDLTestCase):
|
||||
def test_signature(self):
|
||||
sig_i = DDRBuffer.Signature("i", 4)
|
||||
self.assertEqual(sig_i.direction, Direction.Input)
|
||||
self.assertEqual(sig_i.width, 4)
|
||||
self.assertEqual(sig_i.members, wiring.SignatureMembers({
|
||||
"i": wiring.In(data.ArrayLayout(4, 2)),
|
||||
}))
|
||||
sig_o = DDRBuffer.Signature("o", 4)
|
||||
self.assertEqual(sig_o.direction, Direction.Output)
|
||||
self.assertEqual(sig_o.width, 4)
|
||||
self.assertEqual(sig_o.members, wiring.SignatureMembers({
|
||||
"o": wiring.Out(data.ArrayLayout(4, 2)),
|
||||
"oe": wiring.Out(1, init=1),
|
||||
}))
|
||||
sig_io = DDRBuffer.Signature("io", 4)
|
||||
self.assertEqual(sig_io.direction, Direction.Bidir)
|
||||
self.assertEqual(sig_io.width, 4)
|
||||
self.assertEqual(sig_io.members, wiring.SignatureMembers({
|
||||
"i": wiring.In(data.ArrayLayout(4, 2)),
|
||||
"o": wiring.Out(data.ArrayLayout(4, 2)),
|
||||
"oe": wiring.Out(1, init=0),
|
||||
}))
|
||||
self.assertNotEqual(sig_i, sig_io)
|
||||
self.assertEqual(sig_i, sig_i)
|
||||
self.assertRepr(sig_io, "DDRBuffer.Signature(Direction.Bidir, 4)")
|
||||
|
||||
def test_construct(self):
|
||||
io = IOPort(4)
|
||||
port = SingleEndedPort(io)
|
||||
buf = DDRBuffer("i", port)
|
||||
self.assertEqual(buf.direction, Direction.Input)
|
||||
self.assertIs(buf.port, port)
|
||||
self.assertRepr(buf.signature, "DDRBuffer.Signature(Direction.Input, 4).flip()")
|
||||
self.assertEqual(buf.i_domain, "sync")
|
||||
with self.assertRaisesRegex(AttributeError,
|
||||
r"^Input buffer doesn't have an output domain$"):
|
||||
buf.o_domain
|
||||
buf = DDRBuffer("i", port, i_domain="inp")
|
||||
self.assertEqual(buf.i_domain, "inp")
|
||||
buf = DDRBuffer("o", port)
|
||||
self.assertEqual(buf.direction, Direction.Output)
|
||||
self.assertIs(buf.port, port)
|
||||
self.assertRepr(buf.signature, "DDRBuffer.Signature(Direction.Output, 4).flip()")
|
||||
self.assertEqual(buf.o_domain, "sync")
|
||||
with self.assertRaisesRegex(AttributeError,
|
||||
r"^Output buffer doesn't have an input domain$"):
|
||||
buf.i_domain
|
||||
buf = DDRBuffer("o", port, o_domain="out")
|
||||
self.assertEqual(buf.o_domain, "out")
|
||||
buf = DDRBuffer("io", port)
|
||||
self.assertEqual(buf.direction, Direction.Bidir)
|
||||
self.assertIs(buf.port, port)
|
||||
self.assertRepr(buf.signature, "DDRBuffer.Signature(Direction.Bidir, 4).flip()")
|
||||
self.assertEqual(buf.i_domain, "sync")
|
||||
self.assertEqual(buf.o_domain, "sync")
|
||||
buf = DDRBuffer("io", port, i_domain="input", o_domain="output")
|
||||
self.assertEqual(buf.i_domain, "input")
|
||||
self.assertEqual(buf.o_domain, "output")
|
||||
|
||||
def test_construct_wrong(self):
|
||||
io = IOPort(4)
|
||||
port = SingleEndedPort(io)
|
||||
port_i = SingleEndedPort(io, direction="i")
|
||||
port_o = SingleEndedPort(io, direction="o")
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^'port' must be a 'PortLike', not \(io-port io\)$"):
|
||||
DDRBuffer("io", io)
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Input port cannot be used with Bidir buffer$"):
|
||||
DDRBuffer("io", port_i)
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Output port cannot be used with Input buffer$"):
|
||||
DDRBuffer("i", port_o)
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Input buffer doesn't have an output domain$"):
|
||||
DDRBuffer("i", port, o_domain="output")
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Output buffer doesn't have an input domain$"):
|
||||
DDRBuffer("o", port, i_domain="input")
|
||||
|
||||
|
||||
class PinSignatureTestCase(FHDLTestCase):
|
||||
def assertSignatureEqual(self, signature, expected):
|
||||
self.assertEqual(signature.members, Signature(expected).members)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue