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back.rtlil: only translate switch tests once.

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This seems to affect synthesis with Yosys but only marginally.
It is mostly a speed and readability improvement.
This commit is contained in:
whitequark 2018-12-23 07:17:33 +00:00
parent 4e49772f67
commit 45a474788c
1 changed files with 7 additions and 1 deletions
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8
nmigen/back/rtlil.py
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@ -529,6 +529,8 @@ class _StatementCompiler(xfrm.StatementVisitor):
self._group = None
self._case = None
self._test_cache = {}
@contextmanager
def case(self, switch, value):
try:
@ -556,7 +558,11 @@ class _StatementCompiler(xfrm.StatementVisitor):
self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec)
def on_Switch(self, stmt):
with self._case.switch(self.rhs_compiler(stmt.test)) as switch:
if stmt not in self._test_cache:
self._test_cache[stmt] = self.rhs_compiler(stmt.test)
test_sigspec = self._test_cache[stmt]
with self._case.switch(test_sigspec) as switch:
for value, stmts in stmt.cases.items():
with self.case(switch, value):
self.on_statements(stmts)