Catherine
parent
597b1b8839
commit
475b0f35dd
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@ -1,67 +0,0 @@
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import warnings
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warnings.warn("the `amaranth.lib.scheduler` module will be removed without a replacement; "
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"copy the module into your project to continue using it",
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DeprecationWarning, stacklevel=2)
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from .. import *
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__all__ = ["RoundRobin"]
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class RoundRobin(Elaboratable):
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"""Round-robin scheduler.
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For a given set of requests, the round-robin scheduler will
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grant one request. Once it grants a request, if any other
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requests are active, it grants the next active request with
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a greater number, restarting from zero once it reaches the
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highest one.
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Use :class:`EnableInserter` to control when the scheduler
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is updated.
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Parameters
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----------
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count : int
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Number of requests.
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Attributes
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----------
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requests : Signal(count), in
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Set of requests.
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grant : Signal(range(count)), out
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Number of the granted request. Does not change if there are no
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active requests.
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valid : Signal(), out
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Asserted if grant corresponds to an active request. Deasserted
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otherwise, i.e. if no requests are active.
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"""
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def __init__(self, *, count):
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if not isinstance(count, int) or count < 0:
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raise ValueError("Count must be a non-negative integer, not {!r}"
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.format(count))
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self.count = count
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self.requests = Signal(count)
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self.grant = Signal(range(count))
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self.valid = Signal()
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def elaborate(self, platform):
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m = Module()
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with m.Switch(self.grant):
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for i in range(self.count):
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with m.Case(i):
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for pred in reversed(range(i)):
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with m.If(self.requests[pred]):
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m.d.sync += self.grant.eq(pred)
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for succ in reversed(range(i + 1, self.count)):
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with m.If(self.requests[succ]):
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m.d.sync += self.grant.eq(succ)
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m.d.sync += self.valid.eq(self.requests.any())
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return m
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@ -15,6 +15,14 @@ Language changes
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* Removed: (deprecated in 0.4) :meth:`Const.normalize`. (`RFC 5`_)
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Standard library changes
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------------------------
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.. currentmodule:: amaranth.lib
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* Removed: (deprecated in 0.4) :mod:`amaranth.lib.scheduler`. (`RFC 19`_)
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Version 0.4
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===========
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@ -1,99 +0,0 @@
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# amaranth: UnusedElaboratable=no
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import unittest
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import warnings
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from amaranth.hdl import *
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from amaranth.asserts import *
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from amaranth.sim import *
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with warnings.catch_warnings():
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warnings.filterwarnings(action="ignore", category=DeprecationWarning)
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from amaranth.lib.scheduler import *
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from .utils import *
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class RoundRobinTestCase(unittest.TestCase):
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def test_count(self):
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dut = RoundRobin(count=32)
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self.assertEqual(dut.count, 32)
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self.assertEqual(len(dut.requests), 32)
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self.assertEqual(len(dut.grant), 5)
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def test_wrong_count(self):
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with self.assertRaisesRegex(ValueError, r"Count must be a non-negative integer, not 'foo'"):
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dut = RoundRobin(count="foo")
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with self.assertRaisesRegex(ValueError, r"Count must be a non-negative integer, not -1"):
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dut = RoundRobin(count=-1)
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class RoundRobinSimulationTestCase(unittest.TestCase):
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def test_count_one(self):
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dut = RoundRobin(count=1)
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sim = Simulator(dut)
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def process():
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yield dut.requests.eq(0)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertFalse((yield dut.valid))
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yield dut.requests.eq(1)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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sim.add_sync_process(process)
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sim.add_clock(1e-6)
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with sim.write_vcd("test.vcd"):
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sim.run()
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def test_transitions(self):
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dut = RoundRobin(count=3)
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sim = Simulator(dut)
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def process():
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yield dut.requests.eq(0b111)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 1)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b110)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 2)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b010)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 1)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b011)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b001)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b101)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 2)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b100)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 2)
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self.assertTrue((yield dut.valid))
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yield dut.requests.eq(0b000)
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yield; yield Delay(1e-8)
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self.assertFalse((yield dut.valid))
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yield dut.requests.eq(0b001)
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yield; yield Delay(1e-8)
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self.assertEqual((yield dut.grant), 0)
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self.assertTrue((yield dut.valid))
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sim.add_sync_process(process)
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sim.add_clock(1e-6)
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with sim.write_vcd("test.vcd"):
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sim.run()
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