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hdl.ir: rename .get_fragment() to .elaborate().

Browse source 
Closes #9.
This commit is contained in:
whitequark 2019-01-26 02:31:12 +00:00
parent 4922a73c5d
commit 4948162f33
28 changed files with 108 additions and 88 deletions
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4
examples/alu.py
View file

@ -10,7 +10,7 @@ class ALU:
self.o = Signal(width)
self.co = Signal()
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
with m.If(self.sel == 0b00):
m.d.comb += self.o.eq(self.a | self.b)
@ -20,7 +20,7 @@ class ALU:
m.d.comb += self.o.eq(self.a ^ self.b)
with m.Else():
m.d.comb += Cat(self.o, self.co).eq(self.a - self.b)
return m.lower(platform)
return m
if __name__ == "__main__":

12
examples/alu_hier.py
View file

@ -8,10 +8,10 @@ class Adder:
self.b = Signal(width)
self.o = Signal(width)
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.d.comb += self.o.eq(self.a + self.b)
return m.lower(platform)
return m
class Subtractor:
@ -20,10 +20,10 @@ class Subtractor:
self.b = Signal(width)
self.o = Signal(width)
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.d.comb += self.o.eq(self.a - self.b)
return m.lower(platform)
return m
class ALU:
@ -36,7 +36,7 @@ class ALU:
self.add = Adder(width)
self.sub = Subtractor(width)
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.submodules.add = self.add
m.submodules.sub = self.sub
@ -50,7 +50,7 @@ class ALU:
m.d.comb += self.o.eq(self.sub.o)
with m.Else():
m.d.comb += self.o.eq(self.add.o)
return m.lower(platform)
return m
if __name__ == "__main__":

6
examples/arst.py
View file

@ -7,15 +7,15 @@ class ClockDivisor:
self.v = Signal(factor)
self.o = Signal()
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return m.lower(platform)
return m
if __name__ == "__main__":
ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None)
frag = ctr.elaborate(platform=None)
frag.add_domains(ClockDomain("sync", async_reset=True))
main(frag, ports=[ctr.o])

4
examples/ctr.py
View file

@ -7,11 +7,11 @@ class Counter:
self.v = Signal(width, reset=2**width-1)
self.o = Signal()
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return m.lower(platform)
return m
ctr = Counter(width=16)

4
examples/ctr_ce.py
View file

@ -8,7 +8,7 @@ class Counter:
self.o = Signal()
self.ce = Signal()
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
@ -16,7 +16,7 @@ class Counter:
ctr = Counter(width=16)
frag = ctr.get_fragment(platform=None)
frag = ctr.elaborate(platform=None)
# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))

4
examples/fsm.py
View file

@ -12,7 +12,7 @@ class UARTReceiver:
self.ack = Signal()
self.err = Signal()
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
ctr = Signal(max=self.divisor)
@ -56,7 +56,7 @@ class UARTReceiver:
with m.State("ERROR"):
pass
return m.lower(platform)
return m
if __name__ == "__main__":

4
examples/gpio.py
View file

@ -8,12 +8,12 @@ class GPIO:
self.pins = pins
self.bus = bus
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.d.comb += self.bus.r_data.eq(self.pins[self.bus.addr])
with m.If(self.bus.we):
m.d.sync += self.pins[self.bus.addr].eq(self.bus.w_data)
return m.lower(platform)
return m
if __name__ == "__main__":

4
examples/inst.py
View file

@ -9,7 +9,7 @@ class System:
self.dat_w = Signal(8)
self.we = Signal()
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.submodules.cpu = Instance("CPU",
p_RESET_ADDR=0xfff0,
@ -18,7 +18,7 @@ class System:
o_d_dat_w=self.dat_w,
i_d_we =self.we,
)
return m.lower(platform)
return m
if __name__ == "__main__":

4
examples/mem.py
View file

@ -10,7 +10,7 @@ class RegisterFile:
self.we = Signal()
self.mem = Memory(width=8, depth=16, init=[0xaa, 0x55])
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.submodules.rdport = rdport = self.mem.read_port()
m.submodules.wrport = wrport = self.mem.write_port()
@ -21,7 +21,7 @@ class RegisterFile:
wrport.data.eq(self.dat_w),
wrport.en.eq(self.we),
]
return m.lower(platform)
return m
if __name__ == "__main__":

4
examples/pmux.py
View file

@ -10,7 +10,7 @@ class ParMux:
self.c = Signal(width)
self.o = Signal(width)
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
with m.Switch(self.s):
with m.Case("--1"):
@ -21,7 +21,7 @@ class ParMux:
m.d.comb += self.o.eq(self.c)
with m.Case():
m.d.comb += self.o.eq(0)
return m.lower(platform)
return m
if __name__ == "__main__":

5
nmigen/back/pysim.py
View file

@ -347,7 +347,7 @@ class _StatementCompiler(StatementVisitor):
class Simulator:
def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
self._fragment = fragment
self._fragment = Fragment.get(fragment, platform=None)
self._signal_slots = SignalDict() # Signal -> int/slot
self._slot_signals = list() # int/slot -> Signal
@ -386,9 +386,6 @@ class Simulator:
self._run_called = False
while not isinstance(self._fragment, Fragment):
self._fragment = self._fragment.get_fragment(platform=None)
@staticmethod
def _check_process(process):
if inspect.isgeneratorfunction(process):

5
nmigen/cli.py
View file

@ -1,5 +1,6 @@
import argparse
from .hdl.ir import Fragment
from .back import rtlil, verilog, pysim
@ -42,7 +43,7 @@ def main_parser(parser=None):
def main_runner(parser, args, design, platform=None, name="top", ports=()):
if args.action == "generate":
fragment = design.get_fragment(platform=platform)
fragment = Fragment.get(design, platform)
generate_type = args.generate_type
if generate_type is None and args.generate_file:
if args.generate_file.name.endswith(".v"):
@ -61,7 +62,7 @@ def main_runner(parser, args, design, platform=None, name="top", ports=()):
print(output)
if args.action == "simulate":
fragment = design.get_fragment(platform=platform)
fragment = Fragment.get(design, platform)
with pysim.Simulator(fragment,
vcd_file=args.vcd_file,
gtkw_file=args.gtkw_file,

2
nmigen/compat/fhdl/specials.py
View file

@ -57,7 +57,7 @@ class _MemoryPort(CompatModule):
@extend(NativeMemory)
@deprecated("it is not necessary or permitted to add Memory as a special or submodule")
def get_fragment(self, platform):
def elaborate(self, platform):
return Fragment()

3
nmigen/compat/fhdl/verilog.py
View file

@ -1,5 +1,6 @@
import warnings
from ...hdl import Fragment
from ...back import verilog
from .conv_output import ConvOutput
@ -16,7 +17,7 @@ def convert(fi, ios=None, name="top", special_overrides=dict(),
# TODO: attr_translate
v_output = verilog.convert(
fragment=fi.get_fragment().get_fragment(platform=None),
fragment=Fragment.get(fi.get_fragment(), platform=None),
name=name,
ports=ios or (),
ensure_sync_exists=create_clock_domains

2
nmigen/compat/sim/__init__.py
View file

@ -12,7 +12,7 @@ def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name
assert not special_overrides
if hasattr(fragment_or_module, "get_fragment"):
fragment = fragment_or_module.get_fragment().get_fragment(platform=None)
fragment = fragment_or_module.get_fragment()
else:
fragment = fragment_or_module

28
nmigen/hdl/dsl.py
View file

@ -3,7 +3,7 @@ from collections.abc import Iterable
from contextlib import contextmanager
import warnings
from ..tools import flatten, bits_for
from ..tools import flatten, bits_for, deprecated
from .ast import *
from .ir import *
from .xfrm import *
@ -367,9 +367,15 @@ class Module(_ModuleBuilderRoot):
self._statements.append(assign)
def _add_submodule(self, submodule, name=None):
if not hasattr(submodule, "get_fragment"):
raise TypeError("Trying to add '{!r}', which does not implement .get_fragment(), as "
"a submodule".format(submodule))
if not hasattr(submodule, "elaborate"):
if hasattr(submodule, "get_fragment"): # :deprecated:
warnings.warn("Adding '{!r}', which implements .get_fragment() but not "
".elaborate(), as a submodule. .get_fragment() is deprecated, "
"and .elaborate() should be provided instead.".format(submodule),
DeprecationWarning, stacklevel=2)
else:
raise TypeError("Trying to add '{!r}', which does not implement .elaborate(), as "
"a submodule".format(submodule))
self._submodules.append((submodule, name))
def _add_domain(self, cd):
@ -379,12 +385,20 @@ class Module(_ModuleBuilderRoot):
while self._ctrl_stack:
self._pop_ctrl()
def lower(self, platform):
@deprecated("`m.get_fragment(...)` is deprecated; use `m` instead")
def get_fragment(self, platform): # :deprecated:
return self.elaborate(platform)
@deprecated("`m.lower(...)` is deprecated; use `m` instead")
def lower(self, platform): # :deprecated:
return self.elaborate(platform)
def elaborate(self, platform):
self._flush()
fragment = Fragment()
for submodule, name in self._submodules:
fragment.add_subfragment(submodule.get_fragment(platform), name)
fragment.add_subfragment(Fragment.get(submodule, platform), name)
statements = SampleDomainInjector("sync")(self._statements)
fragment.add_statements(statements)
for signal, domain in self._driving.items():
@ -392,5 +406,3 @@ class Module(_ModuleBuilderRoot):
fragment.add_domains(self._domains)
fragment.generated.update(self._generated)
return fragment
get_fragment = lower

10
nmigen/hdl/ir.py
View file

@ -14,6 +14,14 @@ class DriverConflict(UserWarning):
class Fragment:
@staticmethod
def get(obj, platform):
if isinstance(obj, Fragment):
return obj
if not hasattr(obj, "elaborate"): # :deprecated:
return Fragment.get(obj.get_fragment(platform), platform)
return Fragment.get(obj.elaborate(platform), platform)
def __init__(self):
self.ports = SignalDict()
self.drivers = OrderedDict()
@ -105,7 +113,7 @@ class Fragment:
item, = path
return self.generated[item]
def get_fragment(self, platform):
def elaborate(self, platform):
return self
def _merge_subfragment(self, subfragment):

4
nmigen/hdl/mem.py
View file

@ -91,7 +91,7 @@ class ReadPort:
else:
self.en = Const(1)
def get_fragment(self, platform):
def elaborate(self, platform):
f = Instance("$memrd",
p_MEMID=self.memory,
p_ABITS=self.addr.nbits,
@ -154,7 +154,7 @@ class WritePort:
self.en = Signal(memory.width // granularity,
name="{}_w_en".format(memory.name))
def get_fragment(self, platform):
def elaborate(self, platform):
f = Instance("$memwr",
p_MEMID=self.memory,
p_ABITS=self.addr.nbits,

4
nmigen/lib/cdc.py
View file

@ -14,7 +14,7 @@ class MultiReg:
reset=reset, reset_less=True, attrs={"no_retiming": True})
for i in range(n)]
def get_fragment(self, platform):
def elaborate(self, platform):
if hasattr(platform, "get_multi_reg"):
return platform.get_multi_reg(self)
@ -22,4 +22,4 @@ class MultiReg:
for i, o in zip((self.i, *self._regs), self._regs):
m.d[self.odomain] += o.eq(i)
m.d.comb += self.o.eq(self._regs[-1])
return m.lower(platform)
return m

20
nmigen/lib/coding.py
View file

@ -37,7 +37,7 @@ class Encoder:
self.o = Signal(max=max(2, width))
self.n = Signal()
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
with m.Switch(self.i):
for j in range(self.width):
@ -45,7 +45,7 @@ class Encoder:
m.d.comb += self.o.eq(j)
with m.Case():
m.d.comb += self.n.eq(1)
return m.lower(platform)
return m
class PriorityEncoder:
@ -76,13 +76,13 @@ class PriorityEncoder:
self.o = Signal(max=max(2, width))
self.n = Signal()
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
for j in reversed(range(self.width)):
with m.If(self.i[j]):
m.d.comb += self.o.eq(j)
m.d.comb += self.n.eq(self.i == 0)
return m.lower(platform)
return m
class Decoder:
@ -112,7 +112,7 @@ class Decoder:
self.n = Signal()
self.o = Signal(width)
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
with m.Switch(self.i):
for j in range(len(self.o)):
@ -120,7 +120,7 @@ class Decoder:
m.d.comb += self.o.eq(1 << j)
with m.If(self.n):
m.d.comb += self.o.eq(0)
return m.lower(platform)
return m
class PriorityDecoder(Decoder):
@ -151,10 +151,10 @@ class GrayEncoder:
self.i = Signal(width)
self.o = Signal(width)
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.d.comb += self.o.eq(self.i ^ self.i[1:])
return m.lower(platform)
return m
class GrayDecoder:
@ -178,9 +178,9 @@ class GrayDecoder:
self.i = Signal(width)
self.o = Signal(width)
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.d.comb += self.o[-1].eq(self.i[-1])
for i in reversed(range(self.width - 1)):
m.d.comb += self.o[i].eq(self.o[i + 1] ^ self.i[i])
return m.lower(platform)
return m

16
nmigen/lib/fifo.py
View file

@ -138,7 +138,7 @@ class SyncFIFO(FIFOInterface):
self.level = Signal(max=depth + 1)
self.replace = Signal()
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.d.comb += [
self.writable.eq(self.level != self.depth),
@ -206,7 +206,7 @@ class SyncFIFO(FIFOInterface):
with m.If(produce < consume):
m.d.comb += Assert(self.level == (self.depth + produce - consume))
return m.lower(platform)
return m
class SyncFIFOBuffered(FIFOInterface):
@ -237,7 +237,7 @@ class SyncFIFOBuffered(FIFOInterface):
self.level = Signal(max=depth + 1)
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
# Effectively, this queue treats the output register of the non-FWFT inner queue as
@ -262,7 +262,7 @@ class SyncFIFOBuffered(FIFOInterface):
m.d.comb += self.level.eq(fifo.level + self.readable)
return m.lower(platform)
return m
class AsyncFIFO(FIFOInterface):
@ -290,7 +290,7 @@ class AsyncFIFO(FIFOInterface):
except ValueError as e:
raise ValueError("AsyncFIFO only supports power-of-2 depths") from e
def get_fragment(self, platform):
def elaborate(self, platform):
# The design of this queue is the "style #2" from Clifford E. Cummings' paper "Simulation
# and Synthesis Techniques for Asynchronous FIFO Design":
# http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
@ -347,7 +347,7 @@ class AsyncFIFO(FIFOInterface):
self.dout.eq(rdport.data),
]
return m.lower(platform)
return m
class AsyncFIFOBuffered(FIFOInterface):
@ -373,7 +373,7 @@ class AsyncFIFOBuffered(FIFOInterface):
def __init__(self, width, depth):
super().__init__(width, depth, fwft=True)
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.submodules.unbuffered = fifo = AsyncFIFO(self.width, self.depth - 1)
@ -391,4 +391,4 @@ class AsyncFIFOBuffered(FIFOInterface):
m.d.comb += \
fifo.re.eq(1)
return m.lower(platform)
return m

6
nmigen/lib/io.py
View file

@ -17,7 +17,7 @@ class TSTriple:
def __len__(self):
return len(self.o)
def get_fragment(self, platform):
def elaborate(self, platform):
return Fragment()
def get_tristate(self, io):
@ -29,7 +29,7 @@ class Tristate:
self.triple = triple
self.io = io
def get_fragment(self, platform):
def elaborate(self, platform):
if hasattr(platform, "get_tristate"):
return platform.get_tristate(self.triple, self.io)
@ -42,6 +42,6 @@ class Tristate:
o_Y=self.io,
)
f = m.lower(platform)
f = m.elaborate(platform)
f.flatten = True
return f

10
nmigen/test/test_hdl_dsl.py
View file

@ -122,7 +122,7 @@ class DSLTestCase(FHDLTestCase):
m.d.sync += o1.eq(Past(i))
m.d.pix += o2.eq(Past(i))
m.d.pix += o3.eq(Past(i, domain="sync"))
f = m.lower(platform=None)
f = m.elaborate(platform=None)
self.assertRepr(f.statements, """
(
(eq (sig o1) (sample (sig i) @ sync[1]))
@ -386,7 +386,7 @@ class DSLTestCase(FHDLTestCase):
"(sig b)": "sync",
})
frag = m.lower(platform=None)
frag = m.elaborate(platform=None)
fsm = frag.find_generated("fsm")
self.assertIsInstance(fsm.state, Signal)
self.assertEqual(fsm.encoding, OrderedDict({
@ -508,10 +508,10 @@ class DSLTestCase(FHDLTestCase):
def test_submodule_wrong(self):
m = Module()
with self.assertRaises(TypeError,
msg="Trying to add '1', which does not implement .get_fragment(), as a submodule"):
msg="Trying to add '1', which does not implement .elaborate(), as a submodule"):
m.submodules.foo = 1
with self.assertRaises(TypeError,
msg="Trying to add '1', which does not implement .get_fragment(), as a submodule"):
msg="Trying to add '1', which does not implement .elaborate(), as a submodule"):
m.submodules += 1
def test_domain_named_implicit(self):
@ -533,7 +533,7 @@ class DSLTestCase(FHDLTestCase):
m2.d.sync += self.c3.eq(self.s3)
m1.submodules.foo = m2
f1 = m1.lower(platform=None)
f1 = m1.elaborate(platform=None)
self.assertRepr(f1.statements, """
(
(eq (sig c1) (sig s1))

4
nmigen/test/test_hdl_ir.py
View file

@ -474,8 +474,8 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
def setUp_memory(self):
self.m = Memory(width=8, depth=4)
self.fr = self.m.read_port().get_fragment(platform=None)
self.fw = self.m.write_port().get_fragment(platform=None)
self.fr = self.m.read_port().elaborate(platform=None)
self.fw = self.m.write_port().elaborate(platform=None)
self.f1 = Fragment()
self.f2 = Fragment()
self.f2.add_subfragment(self.fr)

8
nmigen/test/test_lib_coding.py
View file

@ -88,7 +88,7 @@ class ReversibleSpec:
self.decoder_cls = decoder_cls
self.coder_args = args
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
enc, dec = self.encoder_cls(*self.coder_args), self.decoder_cls(*self.coder_args)
m.submodules += enc, dec
@ -96,7 +96,7 @@ class ReversibleSpec:
dec.i.eq(enc.o),
Assert(enc.i == dec.o)
]
return m.lower(platform)
return m
class HammingDistanceSpec:
@ -105,7 +105,7 @@ class HammingDistanceSpec:
self.encoder_cls = encoder_cls
self.coder_args = args
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
enc1, enc2 = self.encoder_cls(*self.coder_args), self.encoder_cls(*self.coder_args)
m.submodules += enc1, enc2
@ -113,7 +113,7 @@ class HammingDistanceSpec:
Assume(enc1.i + 1 == enc2.i),
Assert(sum(enc1.o ^ enc2.o) == self.distance)
]
return m.lower(platform)
return m
class GrayCoderTestCase(FHDLTestCase):

14
nmigen/test/test_lib_fifo.py
View file

@ -11,7 +11,7 @@ from ..lib.fifo import *
class FIFOSmokeTestCase(FHDLTestCase):
def assertSyncFIFOWorks(self, fifo, xfrm=lambda x: x):
with Simulator(xfrm(fifo.get_fragment(None)), vcd_file=open("test.vcd", "w")) as sim:
with Simulator(xfrm(Fragment.get(fifo, None)), vcd_file=open("test.vcd", "w")) as sim:
sim.add_clock(1e-6)
def process():
yield from fifo.write(1)
@ -58,7 +58,7 @@ class FIFOModel(FIFOInterface):
self.replace = Signal()
self.level = Signal(max=self.depth + 1)
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
storage = Memory(self.width, self.depth)
@ -101,7 +101,7 @@ class FIFOModel(FIFOInterface):
m.d.comb += Assert(ResetSignal(self.rdomain) == ResetSignal(self.wdomain))
return m.lower(platform)
return m
class FIFOModelEquivalenceSpec:
@ -116,7 +116,7 @@ class FIFOModelEquivalenceSpec:
self.rdomain = rdomain
self.wdomain = wdomain
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.submodules.dut = dut = self.fifo
m.submodules.gold = gold = FIFOModel(dut.width, dut.depth, dut.fwft,
@ -145,7 +145,7 @@ class FIFOModelEquivalenceSpec:
Past(dut.re, domain=self.rdomain))
.implies(dut.dout == gold.dout))
return m.lower(platform)
return m
class FIFOContractSpec:
@ -160,7 +160,7 @@ class FIFOContractSpec:
self.wdomain = wdomain
self.bound = bound
def get_fragment(self, platform):
def elaborate(self, platform):
m = Module()
m.submodules.dut = fifo = self.fifo
@ -224,7 +224,7 @@ class FIFOContractSpec:
m.d.comb += Assume(Rose(ClockSignal(self.wdomain)) |
Rose(ClockSignal(self.rdomain)))
return m.lower(platform)
return m
class FIFOFormalCase(FHDLTestCase):

2
nmigen/test/test_sim.py
View file

@ -238,7 +238,7 @@ class SimulatorUnitTestCase(FHDLTestCase):
class SimulatorIntegrationTestCase(FHDLTestCase):
@contextmanager
def assertSimulation(self, module, deadline=None):
with Simulator(module.lower(platform=None)) as sim:
with Simulator(module.elaborate(platform=None)) as sim:
yield sim
if deadline is None:
sim.run()

3
nmigen/test/tools.py
View file

@ -9,6 +9,7 @@ import warnings
from contextlib import contextmanager
from ..hdl.ast import *
from ..hdl.ir import *
from ..back import rtlil
@ -90,7 +91,7 @@ class FHDLTestCase(unittest.TestCase):
mode=mode,
depth=depth,
script=script,
rtlil=rtlil.convert(spec.get_fragment("formal"))
rtlil=rtlil.convert(Fragment.get(spec, platform="formal"))
)
with subprocess.Popen(["sby", "-f", "-d", spec_name], cwd=spec_dir,
universal_newlines=True,